D I S S E R T A T I O N

Rigorous Integration of Semiconductor
Process and Device Simulators

ausgeführt zum Zwecke der Erlangung des akademischen Grades
eines Doktors der technischen Wissenschaften
eingereicht an der Technischen Universität Wien
Fakultät für Elektrotechnik und Informationstechnik
von

Thomas BINDER

Hütteldorferstraße 52/14
Wien XV

Matrikelnummer 8826314
geboren am 4. Jänner 1969 in Bad-Ischl

Wien, im November 2002

• Abstract
• Kurzfassung
• Acknowledgment
• Contents
• List of Figures
• List of Tables
• Terminology
• 1. Introduction
  • 1.1 Existing Data Models
    • 1.1.1 VISTA
    • 1.1.2 DF-ISE
    • 1.1.3 TIF
    • 1.1.4 Silvaco
    • 1.1.5 SWR -- Semiconductor Wafer Representation
  • 1.2 Outline of this Thesis
• 2. Data Model Aspects for TCAD Simulators
  • 2.1 Requirements for a TCAD Data Model
  • 2.2 Wafer Description
    • 2.2.1 Data in a Persistent Wafer
    • 2.2.2 Operations on the Wafer Data
  • 2.3 Simulator Control
  • 2.4 Classification of Process Steps
  • 2.5 Concept of the WAFER-STATE-SERVER
• 3. WAFER-STATE-SERVER
  • 3.1 Configuration of the WAFER-STATE-SERVER
    • Categorization of Attributes
  • 3.2 I/O layer
    • 3.2.1 WSS -- WAFER-STATE-SERVER ASCII File Format
    • 3.2.2 HDF
    • 3.2.3 FEM
    • 3.2.4 PIF
    • 3.2.5 DF-ISE
  • 3.3 Meshing Layer
    • 3.3.1 TRIANGLE
    • 3.3.2 DELINK
    • 3.3.3 CGG
  • 3.4 Core Data-Structure Layer
    • 3.4.1 Required Functionality
    • 3.4.2 Oct-Tree
    • 3.4.3 Jump-and-Walk
    • 3.4.4 Quad-tree
    • 3.4.5 Binary-Tree
  • 3.5 Integration of Commercial Tools
  • 3.6 Visualization
  • 3.7 Implementation Details
    • 3.A.1 Garbage Collection
    • 3.A.2 Memory Management
• 4. Process Simulation Applications
  • 4.1 MCIMPL-- Three-Dimensional Monte-Carlo Ion Implantation Simulator
    • 4.1.1 Implementation Details
    • 4.1.2 Examples
  • 4.2 FEDOS -- Three-Dimensional Finite-Element Diffusion and Oxidation Simulator
    • 4.2.1 Implementation Details
    • 4.2.2 Examples
  • 4.3 ETCH3D -- Topography Simulator
    • 4.3.1 Implementation Details
    • 4.3.2 Examples
• 5. Optimization for TCAD
  • 5.1 Introduction
    • 5.1.1 Inverse Modeling
    • 5.1.2 Calibration of Models
  • 5.2 Optimization Framework
    • Job Farming Facility
  • 5.3 Gradient Based Optimization Methods
    • Levenberg-Marquardt Optimizer
  • 5.4 Global Optimization Methods
    • 5.4.1 Genetic Optimization Algorithms
    • 5.4.2 Simulated Annealing Algorithms
  • 5.5 Combination of Local and Global Methods
  • 5.6 Examples
    • 5.6.1 Comparison of Local and Global Optimization Strategies
    • 5.6.2 Combination of Local and Global Optimization Strategies
    • 5.6.3 Calibration of a Model for Silicon Self-Interstitial Cluster Formation and
      Dissolution
• 6. Summary
• A. The WAFER-STATE-SERVER API
  • A.1 Instantiating a Wafer Object
  • A.2 Saving Data in a Wafer Object to a File
  • A.3 Updating Data of a Wafer
  • A.4 Querying Data from the Wafer
    • A.4.1 Segment Related Methods
    • A.4.2 Surface Related Methods
    • A.4.3 General Methods of the Wafer Class
    • A.4.4 Methods of the Segment Class
    • A.4.5 Methods of Attribute Class
    • A.4.6 Data and Methods of the Quantity Class
• B. The WSS grammar
  • B.1 Notational Conventions
  • B.2 Definition of the WSS Grammar
    • B.2.1 INFO Section
    • B.2.2 POINTS Section
    • B.2.3 SEGMENTS Section
    • B.2.4 BOUNDARIES Section
    • B.2.5 Example WSS File
  • B.3 Definition of the Config File Grammar.
• C. Automated Selftest
  • C.1 Functionality of VTEST
  • C.2 Configuration of VTEST
    • C.2.1 Defining a Global VTEST Person
    • C.2.2 Defining the Web-Page for VTEST Warning Reports
    • C.2.3 Defining the Platforms for VTEST
    • C.2.4 Defining the Machine for a Certain Architecture
    • C.2.5 Defining the Packages to Test
    • C.2.6 Defining the Tasks to Run
    • C.2.7 Defining Timeouts for the Pre-Defined Tasks
    • C.2.8 Defining the Persons Responsible for a Package
    • C.2.9 Exempting People from Receiving a Report
• Bibliography
• List of Publications
• Curriculum Vitae
• About this document ...

2003-03-27