Ongoing research at the Institute for Microelectronics investigates novel simulation approaches with highly parallel numerical efficiency in mind. This involves the design of semiconductor device and process simulations that can be run on highly parallel workstations, potentially equipped with accelerators and co-processors as well as with thousands of processes, possibly with hundreds of threads each, on supercomputers like the Vienna Scientific Cluster. Where formerly sequential algorithms prevailed, our research results in new parallel variants which significantly outperform their sequential counterparts.
GPU Computing, Supercomputing
High Performance Simulation in Micro- and Nanoelectronics
Review on Sparse Solvers for Exascale Computing
with University of Tennessee and US National Laboratories Argonne, Lawrence Berkeley/Livermore, and Sandia
Shared-Memory Process TCAD
ViennaCL: Parallelized Linear Algebra Routines
with Harvard and ASC/TUW