Process emulation is a relatively recent research direction, when it comes to process TCAD. The general concept is that, very often, physical models of topography motion during deposition and etching are not necessary in order to describe the final surface. Rather, an empirical model can be applied through process emulation. These types of models do not simulate a process in time; instead, they only emulate its outcome. Due to the nature of process emulation models, it is more straight-forward to implement them with explicit surfaces, since they allow for the movement (or drawing) of surfaces and interfaces over large distances, seeing that no time-stepping is required. However, explicit surfaces often require re-meshing and the discretization of the simulation space into voxels, making them undesirable for the emulation of many types of fabrication processes. Furthermore, they are not compatible with physical process simulations, in case that a user would like to perform physical simulation on one set of fabrication steps while emulating other steps. Therefore, we are working on a solution which can be applied over a broad range of geometric descriptions, including the Level Set, making it compatible for integration in a standard process TCAD framework. We apply this with a method called Geometric Advection in order to differentiate it from Transient Advection techniques which involve time-stepping. As an example of the power of Geometric Advection, Fig. 3 (a) shows the emulation results of sausage-chain like structures which are fabricated using several modified deep reactive ion etching (DRIE) steps. To emulate these 80 cycles required less than 15 minutes on a standard desktop PC. Fig. 3 (b) shows an entire SRAM cell in the 5 nm FinFET technology node, which was performed using a combination of physical Monte Carlo based process models (fin patterning, spacer etching, and fin recess), transient topography models (epitaxial growth), and process emulation (shallow trench isolation deposition and etching, dummy gate deposition and patterning, spacer deposition, interlayer dielectric deposition and etching, dummy gate removal, and high-K metal gate deposition). The total time required to simulate the entire cell was less than 16 minutes, 88% of which was required for the physical models.