4.2 Device Design Considerations

A unique distinguishing feature of all semiconductor power devices is their high voltage blocking capability. Depending on the application, the breakdown voltage can range from 25 V for applications such as power supplies to over 6 KV for applications in power transmission and distribution. The ability to support high voltages is determined by the onset of avalanche breakdown, which occurs when the electric field within the device structure becomes strong. In power devices, high electric fields can occur both within the interior regions of the device where current transport takes place and at the edges of the devices. Proper design of devices requires careful attention to field distributions both at the interior and at the edges to ensure high voltage blocking capability. Since the forward voltage drop during current conduction is larger for devices with higher breakdown voltage capability, it is important to obtain a device breakdown voltage as close as possible to the intrinsic capability of the semiconductor material for optimum device performance.

In power devices, the voltage is supported across a depletion layer formed across either a p-n junction, a metal-semiconductor (Schottky barrier) interface, or a metal oxide semiconductor (MOS) interface. The electric field that exists across the depletion layer is responsible for sweeping out holes or electrons that enter this region by the process of either space charge generation or by diffusion from the neighboring quasi-neutral regions. When the voltage is increased, the electric field in the depletion region increases and the mobile carriers are accelerated to higher velocities. The basic p-n structure is the abrupt junction in which the doping concentration on one side of the junction is very large when compared with the other side. In this case the depletion region extends primarily on the lightly doped side of the junction. When the breakdown field of the material is determined, one may calculate the breakdown voltage from [40]:

$$V_\mathrm{B}=\displaystyle\frac{E_\mathrm{B}\cdot W}{2}=\displaystyle\frac {\varepsilon_{s}\cdot E^2_\mathrm{B}}{2{\mathrm{q}}\cdot N_\mathrm{B}}$$ (4.5)

SiC power devices are expected to show superior performance compared to devices made with conventional narrow bandgap semiconductors. This is primarily because SiC has an order of magnitude higher breakdown electric field ( $E_\mathrm{B}=2-4\times 10^6$ V/cm) and higher temperature capability as already discussed in the former chapters. The high breakdown electric field allows the design of SiC power devices with thinner and more heavily doped voltage blocking layers ($W$).

Figure 4.2: Avalanche breakdown voltage as a function of doping concentration (left), and blocking layer thickness as a function of the ideal breakdown voltage (right) for a SiC and a Si abrupt pn junction.

A comparison of the ideal breakdown voltage versus the blocking layer doping concentration ( $N_\mathrm{B}$) is shown in the left side of Fig. 4.2.

The more highly doped blocking layer (more than 10 times higher) provides lower resistance for SiC devices because more majority carriers are present than for comparably rated Si devices. A comparison of the voltage blocking layer thickness for a given breakdown voltage is shown in the right side of Fig. 4.2. The thinner blocking layer of SiC devices (a tenth that of Si devices) also contributes to the lowering of the specific on-resistance by a factor of 10. The combination of a tenth the blocking layer thickness with ten times the doping concentration can yield a SiC device with a factor of 100 advantage in resistance compared to that of Si devices.

In Fig. 4.2 we assume that the semiconductor layer is thick enough to support the reverse-biased depletion layer width $W_\mathrm{m}$ at breakdown. If the semiconductor layer $W$ is smaller than $W_\mathrm{m}$, as shown in Fig. 4.3, the device will be punched through; that is the depletion layer will reach n-n$^+$ interface prior to breakdown. When the reverse bias increases further, the device will break down while the critical field $E_\mathrm{B}$ occurs at $x=0$ is essentially the same.

Figure 4.3: (a) Abrupt p-n junction diode. (b) Electric field distribution.

The breakdown voltage $V^\prime_\mathrm{B}$ for the punch-through diode can be calculated from:

$$\displaystyle\frac{V^\prime_\mathrm... ...aystyle\frac{W}{W_\mathrm{m}}\right)\cdot\left(2-\frac{W}{W_\mathrm{m}}\right).$$ (4.6)

Hence, $V^\prime_\mathrm{B}$ becomes

$$V^\prime_\mathrm{B}=V_\mathrm{B}\cdot\left(\frac{W}{W_\mathrm{m}}\right)\cdot\left(2-\displaystyle\frac{W}{W_\mathrm{m}}\right),$$ (4.7)

here, the depilation layer width $W_\mathrm{m}$ can be obtained from [40]:

$$W_\mathrm{m}= \sqrt{\displaystyle\frac{2\varepsilon_{s}\cdot V_\mathrm{B}}{{\mathrm{q}}\cdot N_\mathrm{B}}}.$$ (4.8)

Punch-through occurs when the doping concentration $N_\mathrm{B}$ in the epilayer becomes sufficiently low. The breakdown voltages for such a diode in $\alpha$-SiC calculated from (4.5) and (4.7) are shown in Fig. 4.4 for 4H-and 6H-SiC. For a given thickness the breakdown voltage approaches a constant value as the doping decreases.

These graphs are used to determine the doping concentration and width of the lightly doped region for obtaining any desired breakdown voltage. The circles on each curve denote the doping that maximizes a performance figure of merit (FOM) for unipolar devices given by the square of the blocking voltage divided by the specific on-resistance [167]

$$\displaystyle\frac{V^2_\mathrm{B}}{R_\mathrm{on,sp}}{\Big\vert}_\... ...X}=\mu_{n}\varepsilon_{s}\left(\displaystyle\frac{2E_\mathrm{B}}{3}\right)^{3}.$$ (4.9)

Since $E_\mathrm{B}$ in SiC is approximately ten times higher, the theoretical maximum for this FOM is about 4 MW/cm$^2$ for silicon and 4000 MW/cm$^2$ for SiC.

Figure 4.4: Breakdown voltage of 4H-SiC (left), and 6H-SiC (right) epilayer as a function of doping concentration and thickness.

T. Ayalew: SiC Semiconductor Devices Technology, Modeling, and Simulation