1. Introduction

THE INCREASING demand for higher computing power, smaller dimensions, and lower power consumption of electronic devices leads to a pressing need to downscale semiconductor components. This process has already led to length scales where the electrical device characteristics is dominated by quantum-mechanical effects. One of the most interesting of these effects is the quantum-mechanical tunneling of charge carriers through classically forbidden regions.

This effect is important for many aspects of microelectronic technology. On the one hand, tunneling currents are exploited in non-volatile memory cells such as EEPROM (electrically erasable programmable read-only memory) or Flash devices to transfer charge to an isolated floating gate by applying high voltages at a capacitively coupled contact. On the other hand, parasitic tunneling currents through the ultra-thin gate dielectric cause increased power consumption of deep-submicron MOS (metal-oxide-semiconductor) transistors. DRAM (dynamical random-access memory) and quasi-nonvolatile SRAM (static random-access memory) cells face reduced retention times due to leakage through the memory node isolation. Resonant tunneling diodes are based on the tunneling mechanism to achieve a negative differential resistance, resulting in extraordinarily high operating frequencies.

It is therefore necessary to account for tunneling effects in the design of semiconductor devices. This can be achieved using numerical simulation. In the field of microelectronics the term TCAD (technology computer-aided design) is used to describe the numerical simulation of the semiconductor manufacturing process and the prediction of the electrical characteristics of the resulting devices. Chapter 2 describes the fundamentals of contemporary CMOS (complementary MOS) technology, gives a brief overview about the crucial topics encountered in device scaling, and outlines the hierarchy of TCAD simulation approaches.

Several models of varying complexity and accuracy can be derived to describe the tunneling current density in semiconductor devices. The models depend on two central quantities, namely the supply function, which describes the supply of available electrons, and the transmission coefficient, which describes the probability that an electron can tunnel through the barrier. The supply function is determined by the energy distribution of the electrons. In equilibrium, this distribution can be approximated by a MAXWELLian distribution.

However, the electric field in miniaturized devices is so high that non-MAXWELLian models have to be be considered to accurately describe the shape of the distribution function and especially the shape of the high-energy tail of the distribution.

To calculate the transmission coefficient of a dielectric layer, SCHRÖDINGER's equation must be solved. One of the most frequently used methods is the WENTZEL-KRAMERS-BRILLOUIN (WKB) approximation which, however, does not reproduce transmission coefficient oscillations as observed in thin gate dielectrics. To accurately describe tunneling through dielectric stacks, it is necessary to resolve the effects of wave function interference. This can be achieved using the transfer-matrix method with either constant or linear potential segments. However, this method is numerically stable only for layer thicknesses up to a few nanometers. It is therefore hardly applicable to the simulation of high-$\kappa$ dielectric stacks, which may have thicknesses of up to 10nm. A more promising approach is the quantum transmitting boundary method which allows a stable and reliable evaluation of the transmission coefficient.

Unlike assumed in idealized models, dielectric layers are not ideal insulators. Caused by electric stress or processing conditions, defects arise in the dielectric which give rise to trap-assisted tunneling. This results in increased tunneling current at low bias, which is referred to as SILC (stress-induced leakage current). The trap-assisted tunneling process is caused by inelastic transitions of carriers supported by the emission of phonons. As this is a transient process it is necessary to account for the creation and annihilation of traps in the dielectric based on the rate equation of the traps.

All these effects are discussed in Chapter 3 which treats the theory of tunneling in semiconductors. This comprises modeling of the supply function, the transmission coefficient, and trap-assisted tunneling.

Modern device simulators are complex software packages and the integration of interfaces to allow tunneling of charge carriers between arbitrary places in a device is not a straightforward task. Chapter 4 provides a short description of the device simulator MINIMOS-NT and summarizes the implementation of the tunneling models. Furthermore, the SCHRÖDINGER solver which is used for the calculation of the transmission coefficient is briefly sketched.

In Chapter 5 several applications are presented. MINIMOS-NT is used for the simulation of gate leakage currents in MOS capacitors and MOSFETs (MOS field-effect transistors). Emphasis is put on the modeling of the different tunneling paths in MOS transistors and on the evaluation of alternative high-$\kappa$ dielectric materials. Furthermore, several NVM (non-volatile memory) devices such as EEPROM devices, trap-rich dielectric, or multi-barrier tunneling based devices are investigated.

Finally, Chapter 6 briefly summarizes the thesis with some conclusions.

A. Gehring: Simulation of Tunneling in Semiconductor Devices