4.1.3.1 BV of P-SOI LDMOSFETs

The simulated BVs of P-SOI LDMOSFETs as a function of the substrate doping concentration $C_\mathrm{sub}$ are shown in Figure 4.4. The BV increases with increasing $C_\mathrm{sub}$ for the P-SOI with a silicon window under the drain, because the RESURF condition of the SOI structure is affected by $C_\mathrm{sub}$ . Below a $C_\mathrm{sub}$ of 4 $\times$ $10^{14}$ $\mathrm{cm}^{-3}$ in this structure, the BV is lower than that of conventional SOI-LDMOSFETs. The solid lines in Figure 4.5 show the electric field near the surface with substrate doping levels of 3 $\times$ $10^{14}$ $\mathrm{cm}^{-3}$ and 1 $\times$ $10^{15}$ $\mathrm{cm}^{-3}$ , respectively.

**Figure 4.4:** BV versus substrate doping concentration of P-SOI LDMOSFETs ( $L_\textrm {d}$ 20 $\mu$ m).
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**Figure 4.5:** Surface electric field for the two different silicon window positions.
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At the gate edge (near the lateral distance of 21 $\mu$ m in Figure 4.5), a high electric field can be seen with a low substrate doping concentration $C_\mathrm{sub}$ of 3 $\times$ $10^{14}$ $\mathrm{cm}^{-3}$ and only a low electric field is found at the drain edge (near the lateral distance of 2 $\mu$ m in Figure 4.5). It means that the RESURF condition strongly depends on $C_\mathrm{sub}$ in this structure. Further increasing $C_\mathrm{sub}$ over 7 $\times$ $10^{14}$ $\mathrm{cm}^{-3}$ reduces the depletion layer width in the substrate region, which decreases the BV (solid line in Figure 4.4). The buried oxide layer does not affect the BV.

In the P-SOI with a silicon window under the source, the RESURF condition does not depend on the substrate doping concentration (from 2 $\times$ $10^{14}$ $\mathrm{cm}^{-3}$ to 1 $\times$ $10^{15}$ $\mathrm{cm}^{-3}$ ) as shown by the dashed lines in Figure 4.4 and Figure 4.5. However, the BV decreases slowly with increasing $C_\mathrm{sub}$ because of the reduced depletion layer width in the substrate region.

**Figure 4.6:** BV versus -drift layer length.
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BV versus

-drift layer length $L_\mathrm{d}$ is shown in Figure 4.6. The maximum BV of the conventional SOI LDMOSFET is 300V at $L_\mathrm{d}$

20 $\mu$ m which does not change by increasing the

-drift layer length from 20 $\mu$ m to 30 $\mu$ m. The maximum voltage is limited by the RESURF condition of the SOI in this structure. In the P-SOI with a silicon window under the drain, the BV is determined by both the RESURF condition and the depletion layer width of the substrate. The maximum BV of this structure is 355V at $C_\mathrm{sub}$

6 $\times$ $10^{14}$ $\mathrm{cm}^{-3}$ and $L_\mathrm{d}$

25 $\mu$ m. The improvement in the voltage handling capability is about 18%. Further increasing $L_\mathrm{d}$ over 30 $\mu$ m decreases the BV by the RESURF condition.

In the P-SOI with a silicon window under the source both, the buried oxide and the depletion region of the substrate, help to increase the BV. A maximum BV of 397V is obtained at $C_\mathrm{sub}$

3 $\times$ $10^{14}$ $\mathrm{cm}^{-3}$ and $L_\mathrm{d}$

30 $\mu$ m. The improvement in the voltage handling capability is about 32% compared to the conventional 300V SOI-LDMOSFET. Because part of the voltage drops in the buried oxide and in the depletion layer in the substrate region, a higher BV is obtained in this structure compared to that of the P-SOI with the silicon window under the drain.