4.2.3.1 Off-State Characteristics and Self-Heating

Figure 4.15 shows the electric field of the conventional SOI-LDMOSFET at $V_\mathrm{DS}$ $=$ 110V, the peak electric fields can be seen at the drain, the field plate, and the gate edge near the surface of the SOI layer. A polysilicon field plate at the gate is employed for reducing the surface electric field near the gate edge [151,152,153,59]. Figure 4.16 shows the electric field of the lateral trench gate SOI-LDMOSFET at $V_\mathrm{DS}$ $=$ 110V. Contrary to conventional RESURF SOI-LDMOSFETs an additional peak of the electric field can be seen at the middle of the lateral trench gate end. With the $n^+$-buffer at the drain the position of the electric field is moved towards the extended drain edge (Figure 4.17).

Figure 4.17 shows the electric field distribution in the lateral trench gate SOI-LDMOSFET along the lateral cross section of the surface and the middle of the SOI layer. The peak electric field can be clearly seen in the middle of the lateral trench gate end. This additional peak helps to decrease the electric field near the gate edge on the top of the SOI layer and increase the depletion area of the device. As a result the BV and leakage current of the proposed device are simultaneously increased compared to the conventional device with the same structure parameters. With an $n$-drift width of 5.5$\mu$m the maximum BV of the lateral trench gate structure is 117V with $N_\mathrm{D}$ $=$ 1.0 $\times$ $10^{16}$ $\mathrm{cm}^{-3}$. The BV of the conventional SOI-LDMOSFET is 112V with the same doping and structure parameters.

Figure 4.18 shows the leakage currents of lateral trench gate SOI-LDMOSFETs versus drain voltage as a function of the lattice temperature up to 573K. The shape of the leakage current does not change significantly with temperature, but the BV increases. The increase of BV is caused by the reduction of the mean free path of the carriers due to lattice scattering, requiring a higher field to initiate impact ionization. Generally, there are two components - a generation current and a diffusion leakage current - responsible for the leakage current under reverse bias conditions. The generation current is a function of depletion layer width, intrinsic carrier concentration, and carrier lifetime. The generation current increases with increasing reverse bias. The diffusion leakage current is determined by the minority carrier generation at the depletion boundaries. It decreases with increasing doping concentration and it strongly depends on the temperature.

Figure 4.15: Electric field distribution of the conventional SOI-LDMOSFET at $V_\textrm {DS}$ $=$ 110 V. A higher electric field can be seen at the drain and gate edges near the surface of the SOI.

Figure 4.16: Electric field distribution of the lateral trench gate SOI-LDMOSFET at $V_\textrm {DS}$ $=$ 110 V. A higher electric field can be seen at the drain edge and in the middle of the lateral trench gate.

Figure 4.17: Electric field in the lateral trench gate SOI-LDMOSFET along the lateral cross section of the surface and the middle of the SOI layer.

Figure 4.18: BV versus lattice temperature of the lateral trench gate SOI-LDMOSFET.

Figure 4.19: Comparison of the temperature increase by self-heating between the conventional and lateral trench gate SOI-LDMOSFET near the surface of the SOI layer.

The temperature distribution inside a device due to self-heating is determined by the heat generation profile and the thermal conduction inside SOI-LDMOSFETs [103,104,154,155]. In majority carrier devices such as MOSFETs, there is very little carrier recombination and as a result heat generation is mainly caused by Joule heating. It is proportional to the local resistances of the n-drift and channel region. However, the channel resistance of the high-voltage devices (generally over 100V) is not dominant in the on-resistance.

Figure 4.19 shows the temperature distributions near the SOI surface of the conventional and lateral trench gate SOI-LDMOSFETs with an applied gate voltage $V_\mathrm{GS}$ $=$ 12V and a drain-source voltage $V_\mathrm{DS}$ $=$ 2V. The bottom of the devices is assumed to be isothermal at 300K. Because of the dominant heat generation at the $n$-drift region (from 2.5 to 8$\mu$m of the figure) the temperature rise is highest near the center of the $n$-drift region, and decreases largely towards source and slightly towards drain. The increased conduction area near the gate compared to that near the drain (see Figure 4.21) causes a further decrease of the temperature towards source. Because of the lower on-resistance (by increasing the current) of the lateral trench gate structure a higher temperature is obtained at the $n$-drift region of the lateral trench gate SOI-LDMOSFET.