4.5.2 Device Structure and Operations

Figure 4.43 shows the schematic structure of the proposed SOI SA-LIGBT. The $n^+$-layer is introduced to the $p^+$-anode region to achieve a shorted-anode structure. As can be seen in the figure, the $n^+$- and $p^+$-areas are separated by the trench oxide.

Figure 4.43: Schematics of the proposed SOI SA-LIGBT with a trench oxide at the drain$/$anode.

The device is designed to achieve a BV of 120V with an SOI thickness $t_\mathrm{soi}$ of 2.0$\mu$m and with a buried oxide thickness $t_\mathrm{ox}$ of 1.0$\mu$m. The design parameters used for this analysis are listed in Table 4.5.

Table 4.5: The technological and geometrical parameters considered for device simulation.

Parameter	Value
$n$-drift doping $N_\mathrm{D}$	1.0 $\times$ $10^{16}$ $\mathrm{cm}^{-3}$
$n$-drift length $L_\mathrm{d}$	8.5$\mu$m
SOI thickness $t_\mathrm{soi}$	2.0$\mu$m
N-substrate doping	5.0 $\times$ $10^{18}$ $\mathrm{cm}^{-3}$
Buried oxide thickness $t_\mathrm{ox}$	1.0$\mu$m
$n^+$ drain length$\mu$m	2.0$\mu$m
$p^+$ anode length$\mu$m	6.0$\mu$m
Trench oxide depth$\mu$m	0.5 - 1.5$\mu$m

The maximum BV of the SOI SA-LIGBT is limited by the thickness of the buried oxide. An optimal drift length and doping must be ensured to get the best trade-off between the on-resistance and the BV. As shown in the table the $n$-drift length is 8.5$\mu$m, the doping amounts to 1.0 $\times$ $10^{16}$ $\mathrm{cm}^{-3}$, and the trench oxide depth is 1.0$\mu$m. A highly doped $n$-buffer is added at the drain/anode region which helps to prevent punch through at this region.

Figure 4.44: Current flow arrows of the proposed SA-LIGBT at $V_\textrm {G}$ $=$ 12 V and $V_\textrm {A}$ $=$ 10 V.

To suppress the NDR the length of the $p^+$-anode of the conventional SA-LIGBT must be increased. To overcome this drawback we introduce a trench oxide at the drain/anode region. The $n^+$-drain length of 2.0$\mu$m and the $p^+$-anode length of 6.0$\mu$m are used through out all the simulations. With the structure proposed it is possible to suppress the NDR without increasing the $p^+$-anode length.

As shown in Figure 4.43, the device has a hybrid LDMOSFET-LIGBT structure with a common drift region. The $p^+$-anode provides conductivity modulation of the $n$-drift region. The $n^+$-drain defines a lateral DMOS structure and an electron extraction path during turn-off of the device. As a result two different modes of on-state operation can be seen, which depend on the bias conditions.

At low anode voltages the device exhibits MOSFET operation. Only the $n^+$-region at the drain/anode contributes to the current conduction in the on-state and significant conductivity modulation of the $n$-drift region cannot be seen. As the anode voltage increases, the potential underneath the $p^+$-anode starts to fall and makes the $p^+$-anode and $n$-drift junction forward biased. Considerable injection of holes from the $p^+$-anode to the $n$-drift region takes place, resulting in a lower forward voltage drop than that of the SOI-LDMOSFET. Figure 4.44 shows the current flow of the proposed SA-LIGBT at $V_\mathrm{G}$ $=$ 12V and $V_\mathrm{A}$ $=$ 10V. The electron current at the $n^+$ drain region, and the hole current at the $p^+$-anode and under the cathode ($p$-body region) can be seen simultaneously.