5.6 Modeling the coupling from integrated circuits

[6] accurately simulated the near field of a microcontroller IC, only utilizing the currents on the package and neglecting the currents on the die. Both [6] and [52] explained that the near field of an IC can be modeled with the currents on the IC package. The near field of the IC is directly related to the IC common mode coupling to the cavity field, as presented in the previous section. Therefore, the common mode coupling of an IC can also be modeled only from the currents on the package. It is also evident that only the vertical segments of the package couple to the cavity, because these segments are large compared to the vertical interconnects on the die. An introduction of the vertical segments from the package interconnects with their associated currents according to the previously described method correctly models the coupling of the IC to the cavity. A standard ICEM model for conducted emission simulations accurately describes the currents and voltages on the package of the device. A freeware tool for ICEM modeling and further IC EMC issues has been presented by [89] and ICEM modeling is described in the ICEM cookbook [90]. ICEM package modeling issues are described in [91][92]. Chip level passive distribution network ICEM modeling was presented in [93][94][95] and dynamic IC switching current ICEM modeling was present in [96][97]. Examples for accurate VLSI ICEM models have been presented by [60] and [61]. The positions and lengths of the vertical package interconnects are obtained from a mechanical package drawing or from CAD data. The lengths of the vertical segments are used to obtain the associated coupling factors d/h for the introduction of the package excitation currents to the cavity model. Package coding is regulated by the JEITA [98] standard EIAJ ED-7303B. The package code includes information about the material of the package body, package specific features, the basic package designation, the package terminal number, the package nominal dimension, and the terminal in-line interval. Table 5.2 contains a list of some basic IC package type designations. All packages, with exception of the BGA type, are lead frame packages. The vertical segments of a lead frame package are the pins and the bond wires, while the vertical segments of a BGA package are the balls, the vias of an interposer PCB, and the vertical bond wire segments.

Table 5.2: Some basic packages type designations.

Acronym	Designation	Lead frame (yes/no)
BGA	Ball Grid Array	no
QFP	Quad Flat Package	yes
SOP	Small Outline Package	yes
DIP	Dual In-Line Package	yes

The package specific feature code, which is added to package designation before the basic designation, determines, among other package properties the seated height of the package. Table 5.3 contains a list of seated hight codes. The maximum seating height determines the maximum possible vertical segment length of a package.

Table 5.3: Seated height package code information.

Seated hight code	Meaning	Maximum seated height
L	Low profile	$1.2mm$	$<$	L	$\leq 1.7mm$
T	Thin	$1.0mm$	$<$	T	$\leq 1.2mm$
V	Very thin	$0.8mm$	$<$	V	$\leq 1.0mm$
W	Very very thin	$0.65mm$	$<$	W	$\leq 0.8mm$
U	Ultra thin	$0.5mm$	$<$	U	$\leq 0.65mm$
X	Extremely thin			X	$\leq 0.5mm$

Thin packages are usually realized utilizing reverse bonding with a bonding wire height lower than 10mil (0.2mm). In the case of very short bonding heights compared to the pin heights of a lead frame package, the bonding wire can be neglected and the enclosure can be modeled only with the coupling segments at the pin positions. However, most packages contain bond wires with similar heights as the lead frame, which cannot be neglected. The bond wires also have to be modeled in BGA type packages. Since the bond wire lengths are usually short, the bond wires can be modeled with a constant height obtained from the mean height of the bond wire shape. The coupling factor 5.9 is expressed with the mean value of the vertical bond wire heights $d_{i}$, weighted with their respective lengths $l_{i}$

$$K_{couple}=\frac{d_{ic}}{h}=\frac{1}{h}\frac{\sum_{i=1}^{s}[d_{i}l_{i}]}{\sum_{i=1}^{s}l_{i}}.$$ (5.17)

$s$ denotes the number of segments with different heights above the PCB ground plane along the bond wire. This enables a simplified model for the cavity coupling of each package pin, especially when the bond wires are short, with low height. This enables an introduction of the bond segments to a median loop with vertical segments only at the pins of the lead frame. A thin QFP package is depicted in Figure 5.12. The high frequency currents on the package and the associated loop with its vertical segments is depicted in Figure 5.13. Note that the return current even of a fast signal might not flow over the ground pin which is closest to the signal pin, when the package has more than one ground pin, because the high ohmic resistances of the interconnects on the die have a significant influence on the overall loop impedance. Therefore, the correct ground pin has to be considered for the introduction into the cavity model. In contrast to a lead frame package, the vertical segments on a BGA package are the lead balls, the vias of the interposer, and the bond wires.

Figure 5.12: Thin QFP package with eight pins, mounted on a PCB.

Current flow path on the PCB, the IC package, and the die. The vertical current segments are on the pins of the leadframe and on the bond wires. The dotted current arrows indicate that the current is flowing on the lower side of the lead frame pins, according to a shorter current loop.

Current loops on the PCB and on the IC package. Introduction of the IC into the cavity model is performed with the vertical current segments of the package current loop at the pins of the leadframe. Median height and length values are used to model the current loop on the package. Note that the vertical bond wire segments can only be included into the median loop, when their height is low. A comparison of the simulation results, with and without explicit modeling of the vertical bond wire segments, should be made to validate the simplified package model.

Figure 5.13: High frequency current flow path on the IC package in Figure 5.12 and the associated loop with its vertical and horizontal current segments. The plastic mold and the remaining pins of the package as depicted in Figure 5.12 have been removed to enable the illustration of the current path.

C. Poschalko: The Simulation of Emission from Printed Circuit Boards under a Metallic Cover