1.2 The Structure of this Work

We will sketch the processing techniques which are involved in the manufacturing of integrated circuits and their associated TCAD simulation tools in . The simulation tools which are available to perform electrical investigations on structural descriptions of semiconductor devices will also be outlined. Furthermore, we will discuss how a fabrication technology can be characterized in a comprehensive manner, based upon models of the fabrication process and electrical modeling of its electronic devices. A brief discussion of process optimization and the calibration of simulation models concludes .

Modeling abstractions is the subject of . It introduces TCAD models which are abstract representation of arbitrary TCAD simulation tools. We will see how SIESTA encapsulates these simulation tools, and how elaborate simulation models can be created.

introduces SIESTA's TCAD experiments. Those TCAD experiments allow users to perform thorough investigations on simulation models. It explains how optimization, calibration, design of experiments (DOE), or statistical analysis can be carried out.

goes into more detail about how SIESTA's TCAD models can be utilized to build simulation models. It gives examples of the encapsulation of simulation tools by models. Furthermore, possibilities for a structured and hierarchical description of simulation problems will be discussed. This will give the reader an idea of the strengths which are intrinsic to TCAD models. is concluded with insight into evaluation mechanisms of TCAD models.

discusses the job farming capabilities of SIESTA. The implications of parallel computation on a cluster of heterogenous workstations are outlined and a load-balancing mechanism for the efficient distribution of simulation workload is explained.

SIESTA's implementation and its core components will be outlined in . It highlights features which contributed to the implementation of a modular simulation environment. Some key components are explained in detail to give the reader an idea of SIESTA's internal structure.

The application of SIESTA's facilities to the optimization of IC fabrication technology is demonstrated in . A comprehensive simulation model of a fabrication technology is explained and an optimization is performed based on that model. The optimization procedure, in particular, how SIESTA is dealing with it, concludes .

shows how inverse modeling can be performed with SIESTA. It describes how calibrations can be carried out with comprehensive sets of measurements. Furthermore, an example demonstrates how SIESTA can be used for inverse modeling of doping profiles on the basis of electrical measurements.