1. Introduction

For more than two decades the rapid progress in complementary metal-oxide-semiconductor (CMOS) technology was accompanied by a tremendous pace of scaling, leading to an enormous increase of the speed and functionality of electronic devices. This trend is expected to continue in the coming decade as predicted and institutionalized by the International Technology Roadmap for Semiconductors [SIA06].

The end of scaling has often been predicted in the past, but engineers' ingenuity has regularly proven wrong these predictions [Haensch06]. Two remarkable failures involve a predicted limit for spatial resolutions of about 400nm imposed by lithography [Hoeneisen72,Wallmark75] and a lower bound of 3nm for the gate oxide thickness, below which an unacceptable gate leakage current was expected [Hu96,Stathis98].

However, when examining high-performance devices in recent technology generations, early signs of scaling limits can be seen. Even though potential brick walls for scaling have been overcome, it is becoming increasingly difficult to meet metal-oxide-semiconductor field-effect transistor (MOSFET) performance gains with reasonable device leakage. To obtain the projected performance enhancement of 30% per generation, device designers have been forced to relax the device subthreshold leakage from one nA/µm for the 250nm node to several hundreds of nA/µm for the 65nm node [Chang03]. Consequently, the gate leakage current constitutes a significant portion of the power budget of microprocessors. Another critical scaling issue involves the increase of the source-drain series resistance resulting from the need for ultra-shallow p-n junctions in the source-drain region [Skotnicki05]. To keep the source-drain series resistance at a reasonable fraction of the total channel resistance (approximately 10%), several alternative MOSFET structures have been proposed, such as non-overlapped gate structures, which do not require ultra-shallow source-drain junctions [Boeuf01,Lee02], or structures with metallic source and drain electrodes to minimize the series resistance [Connelly03,Fritze04,Zhu04].

In the present time the scaling of the gate oxide thickness has halted [Haensch06]. Advanced single gate structures, such as FinFETs, ultra-thin-body (UTB) MOSFETs, or multiple gate MOSFETs might provide a path to scaling CMOS to the end of the ITRS roadmap. Additionally, the material properties of a device are now being included in the scaling analysis. For example, the permittivity constant of the gate insulator has only slightly participated in scaling in the past. This is expected to change with the introduction of metal gates and hafnium-based high-$\kappa$ dielectrics in the 45nm technology node, which will be in mass production this year [Intel07].

Another parameter not included in scaling in the past was the mobility of the channel material. This fact was especially critical, since mobility tends towards lower values due to higher vertical fields in down-scaled MOSFET devices. With the 90nm technology node strain techniques have been introduced that efficiently increased the transistor drive current by enhancing the mobility of carriers in the channel [Rim02,Thompson04].

Strain engineering is a key element in current CMOS technologies and is widely believed to take a key position also in the future, since the benefits caused by mobility enhancement in the channel are comparatively big [Thompson06]. Furthermore, it has been demonstrated that this technology can also be used in non-classical CMOS structures [Rim03,Andrieu06]. For example, the advantages of a UTB MOSFET, such as the better electrostatic control of the channel by the gate in the off-state, can be combined with enhanced carrier transport provided by strain. Therefore, increasing emphasis is put on this technology to enhance chip performance. Since the maximum performance enhancement this new technology can deliver is still not known, it is convenient to do numerical simulations with accurate physical models in order to gain a better understanding of the underlying mechanisms responsible for the observed mobility enhancement. In this thesis, the effect of strain on the band structure of silicon (Si) and the electron mobility enhancement in bulk MOSFETs and UTB MOSFETs is analyzed numerically.

The thesis is organized as follows: In Chapter 2 the reader is introduced to the short but versatile history of CMOS strain engineering. After reviewing the most important global and local strain techniques, several state-of-the-art technologies are outlined. In Chapter 3 the bulk band structure of strained cubic semiconductors is discussed. A kp method capturing the effect of strain on the lowest conduction band of Si is developed. Additionally, the adaptation of the empirical pseudopotential method (EPM) including spin orbit coupling to incorporate strain effects is presented. In Chapter 4 the subband structure of strained Si inversion layers formed at Si-SiO$_2$ interfaces with various substrate orientations is discussed. The subband energies and the wave functions of Si inversion layers are obtained by a self-consistent solution of the Schrödinger equation and the Poisson equation. Chapter 5 is dedicated to the numerical modeling of mobility. The transport properties of strained Si are investigated by solving the semiclassical Boltzmann equation using the Monte Carlo (MC) method. The models for the scattering mechanisms used in the MC simulations of bulk Si and Si inversion layers are given. Additionally, a MC method that includes degeneracy effects for small driving fields is presented. Simulation results are summarized in Chapter 6. The analytical band structure obtained from the kp theory is compared to numerical calculations using the EPM. The subband structure of strained Si inversion layers is presented for various strain configurations and substrate orientations. The simulation results for the bulk electron mobility of strained Si are compared to measurements and to phenomenological mobility models based on the piezoresistance coefficients. The electron mobility is calculated using the MC method employing fullband (FBMC) and analytical band models (ABMC). A comparison of the results allows the extraction of the limits of validity of the analytical band model. Finally, the effect of strain and degeneracy on the effective mobility in Si inversion layers for (001) and (110) substrate orientation is presented and the influence of the Si body thickness on the effective mobility in ultra thin body MOSFETs is discussed.

E. Ungersboeck: Advanced Modelling Aspects of Modern Strained CMOS Technology