2.2.1 Global Strain

Mechanically compressing and/or stretching of the $Si$ crystal lattice introduces strain and can be realized by various means (c.f. Fig. 2.6). In the beginning research was concentrated on biaxial global strain accomplished by a thin epitaxially grown $Si$ layer on a relaxed $SiGe$ virtual substrate [58,59]. Due to the lattice mismatch between $Si$ and $SiGe$, the $Si$ lattice is biaxially tensile strained along the interface plane. For instance, Rim et al. [53] showed a mobility enhancement of $110\,\%$ for electrons and $45\,\%$ for holes in the strained silicon layer for $\{001\}$ oriented substrates on $<100\,\mathrm{nm}$ strained $Si$ MOSFETs.

Layer transfer and wafer bonding techniques allow integration of global strain on SOI substrates. Comparable to wafers without insulating layer electron and hole mobility enhancement has been demonstrated for ultra-thin Strained silicon layer on Silicon-Germanium On Insulator (SSGOI) [60,61,62,63] and Strained Silicon layer Directly On Insulator (SSDOI) [64,65].

Figure 2.6: Scheme for different global strain techniques: 1.) strained silicon layer on $SiGe$ on bulk wafer; 2.) strained silicon layer directly on insulator (SDGOI); 3.) strained silicon layer on $SiGe$ substrate on insulator (SSGOI).

1.)	2.)	3.)

Ultra thin SSGOI is of special interest, due to the removal of the $SiGe$ layer before transistor fabrication. Thus, process-integration problems caused by the $SiGe$ layer can be overcome. Some of these problems are:

• Ge up-diffusion from the $SiGe$ layer reduces the thermal budget window for $SiGe$ on insulator [60].
• A high density of defects is inserted into the neighboring Si layer by $SiGe$ strain relaxation[57].
• $SiGe$ exhibits an enhanced dopant diffusion rate (e.g. B, As)[66].
• SSGOI devices possess lower thermal conductivity, induced by the $SiGe$ layer, and therefore suffer significant device self-heating [67].

Alternatively, the strain can be introduced after the wafer has completely been processed [68,69]. This is realized by thinning the wafer to less than $10\mathrm{\mu m}$ and transferring it to a polymere film. After this, mechanically straining the Si membrane allows uniaxial and biaxial strain parallel to the substrate surface without inducing defects, e.g. interstitials or vacancies, in the Si layer. The mechanically strained wafer can be bonded to a final substrate safely, as long as the strain level stays within the elastic limit. At ultra-low strain levels ( $\sim0.052\%$), mobility $\mu_{\mathrm{eff}}$ improvement of $18.4\%$ and in saturation current of $18.05\%$ was found for n-channel MOSFETs, and $14.35\%$ ($14.56\%$ at saturation current) for p-channel MOSFETs (at $0.031\%$) [68]. Despite it's cost effectiveness there are also yield and reliability issues which hinder the full-scale IC manufacturing application[70].

The major disadvantage of global strain techniques is that they facilitate only one type of strain. Due to the fact that the effective mobility $\mu_{\mathrm{eff}}$ behaves differently for electrons and holes at compressive/tensile strain only one of the mobilities can benefit, while the other is degraded (e.g. compressive biaxial strain can raise the mobility for p-channel MOSFETS, while degrading the mobility of n-channel MOSFETs). This obstacle can be circumvented by local strain techniques which enable different strain types for n-channel and p-channel MOSFETs.