The goal of the ADEQUAT+ project was to develop the following process steps and process modules for 0.25µm CMOS technology and below:
- Interconnects for 0.25µm CMOS, i.e. the 0.25µm Back-end
- Device Modules for 0.18µm CMOS, i.e. the 0.18µm Front-End
- Low-Voltage Optimized Processes in 0.25µm CMOS
- a Low-voltage test circuit in 0.25µm CMOS.
The feasibility of the process modules had to be demonstrated with actual devices and their characterisation needed to be completed. Furthermore, the process know-how needs to be transferred to industrial pilot lines with focus on manufacturability, process sensitivity and cost issues, i.e. standard equipment, simplest possible mask sets, etc.
Major Milestones
• Preliminary process specs and tentative layout rules for 0.25µm interconnects.
• Preliminary process specs and target design rules for 0.18µm front-end.
• First electrical results on 0.18µm devices (NMOST, PMOST).
• First 0.25µm MLM test structures available.
• Report on evaluation of measurement data on power dissipation and performance for 0.25µm low voltage test circuit.
• Updated list of milestones for European submicron CMOS R&D.
ADEQUAT+ is a follow-up project to ADEQUAT-2.
