Yury Illarionov MSc PhD Dr.techn. Publications

Biography Yury Illarionov was born in Leningrad (now Saint-Petersburg) in 1988. He studied solid state physics at the Physical Science and Technology Faculty of St. Petersburg State Polytechnical University where he received the B.Sc. and M.Sc. degrees in 2009 and 2011, respectively. From 2010 to 2012 he studied advanced material science in Grenoble Institute of Technology (France) and University of Augsburg (Germany) in frameworks of Functionalized Advanced Materials and Engineering (FAME) Erasmus Mundus program and in September 2012 received a double European M.Sc. degree. His scientific carrier has started in October 2007 in Ioffe Physical-Technical Institute (Russia) and in November 2011 he joined the PhD program there. He also visited IRCELYON (France, May-July 2011) and Singapore Institute of Manufacturing Technology (Singapore, February-July 2012) as a young guest researcher. He joined the Institute for Microelectronics in February 2013. In January 2015 he received the PhD degree in semiconductor physics from Ioffe Physical-Technical Institute and in December 2015 the Dr.techn. degree from TU Wien. Since January 2016 Dr. Yury Illarionov is a postdoc researcher working on reliability of the next-generation 2D FETs with graphene, MoS2 and phosphorene.

Graphene is a promising material with numerous properties that can be exploited in optoelectronics and sensors. Many of these devices require high-quality insulators to either form graphene FETs (GFETs) or otherwise protect graphene. Previously used amorphous oxides contain numerous border traps which cause severe hysteresis and long-term drifts of the gate transfer characteristics. As a promising alternative, we have demonstrated GFETs with 2 nm thick CaF₂ insulators previously used in the most stable MoS₂ FETs reported so far. CaF₂ is an ionic crystal insulator with good dielectric properties (ε = 8.43, E_G = 12.1 eV) which forms quasi van der Waals interfaces with 2D materials. We have fabricated >100 single-layer GFETs on Si/CaF₂ substrates (Fig. 1a) prepared by our established molecular beam epitaxy method at 250oC. To avoid leakage currents from large contact pads, they have been isolated with 10 nm Al₂O₃ grown by plasma-assisted atomic layer deposition just prior to sputtering of the 25 nm Pd electrodes. Next, a commercial CVD-graphene was transferred onto the substrate by a PMMA-assisted method and patterned by oxygen plasma. The obtained arrays contain hundreds of GFETs with channel dimensions (L×W) from 160 µm×100 µm down to 9 µm×3 µm. Typical ID-VG characteristics (Fig. 1b) exhibit relatively high currents up to 32 µA/µm within a few Volts' operation range due to the significantly downscaled thickness of the gate insulator of only 2 nm. The ID-VD characteristics (Fig. 1c) show good current control with some kinks typical of ambipolar GFETs. In Fig. 2a, we show that, already at this early stage of research, many GFETs with very similar ID-VG characteristics can be obtained. The analysis of IDirac vs. VDirac distributions for 116 studied devices (Fig. 2b) shows that the variability is stronger for smaller channels which are likely more affected by grain boundaries in CVD-graphene. Our results open a route towards mass-production of GFETs with thin crystalline CaF₂ insulators which can be used in the future for many intriguing applications.

Fig. 1: (a) Schematic structure of our back-gated GFETs with 2 nm CaF₂ insulators. (b) Typical I_D-V_G characteristics of these devices. The inset shows that the gate leakage current through our thin CaF₂ layers is small compared to the drain current. (c) The I_D-V_D characteristics measured for the same GFET exhibit some ambipolar kinks.

Fig. 2: (a) I_D-V_G characteristics of 11 similar GFETs with 80µm×50µm channels selected from our total statistics of 116 devices with different channel dimensions. (b) The distribution of I_Dirac vs. V_Dirac for all 116 devices; the number of devices with the corresponding channel dimension is marked in brackets in the legend. The measurements have been done before any annealing step, and some smaller devices have a more positive V_Dirac (for those GFETs we used a V_G sweep range from 0 to 4V).