Improvements in epilayer quality are needed as there are presently many observable defects
present in state of the art SiC homoepilayers. Non-ideal surface morphological features, such
as growth pits, 3C-SiC triangular inclusions (triangle defects) introduced in
Subsection 2.3.3.2, are generally more prevalent in 4H-SiC epilayers than 6H-SiC
epilayers. Most of these features appear to be manifestations of non-optimal step flow during
epilayer growth arising from substrate defects, non-ideal substrate surface finish,
contamination, and/or unoptimized epitaxial growth conditions. While by no means trivial, it
is anticipated that the SiC epilayer surface morphology will greatly improve as refined
substrate preparation and epilayer growth processes are developed. Many impurities and
crystallographic defects found in sublimation-grown SiC wafers do not propagate into SiC
homoepitaxial layers. For example, basal-plane dislocation loops emanating from micropipes and
screw dislocations in sublimation-grown SiC wafers (Subsection 2.3.2.2) are
generally not observed in SiC epilayers. Unfortunately, however, screw dislocations (both
micropipes and closed-core screw dislocations) present in commercial c-axis wafers do
replicate themselves up the crystallographic c-axis into SiC homoepilayers grown on commercial
wafers [51]. Therefore, devices fabricated in commercial epilayers are still subject
to electrical performance and yield limitations imposed by commercial substrate
screw-dislocation defect densities.