2.4.2 Selective Doping- Ion Implantation

The fact that diffusion coefficients of most SiC dopants are negligibly small below $\sim$1800 $^{\circ}$C is advantages for maintaining device junction stability, because dopants do not undesirably diffuse as the device is operated long-term at high temperatures. Unfortunately, this characteristic also precludes the use of conventional dopant diffusion, a highly useful technique widely employed in silicon devices manufacturing, for patterned doping of SiC.

Laterally patterned doping of SiC is carried out by ion implantation. This somewhat restricts the depth that most dopants can be conventionally implanted to less than 1 $\mu$m using conventional dopants and implantation equipment. Compared to silicon processes, SiC ion implantation requires a much higher thermal budget to achieve acceptable dopant activation. Summaries of ion implantation processes for various dopants can be found in [73,74,34]. Most of these processes are based on carrying out implantation at elevated temperatures ($\sim$500 to 800$~^{\circ}$C) using a patterned high-temperature masking material. The elevated temperature during implantation promotes some lattice self-healing during the implantation, so that damage and segregation of displaced silicon and carbon atoms does not become excessive, especially in high-dose implants often employed for ohmic contact formation [73,74]. Coimplantation of carbon with p-type dopants has recently been investigated as a means to improve the electrical conductivity of implanted p-type contact layers [75].

Following implantation the patterning mask is stripped and a much higher temperature ($\sim$1200 to 1800$~^{\circ}$C) anneal is carried out to achieve maximum electrical activation of dopant donor or acceptor ions. The final annealing conditions are crucial to obtaining the desired electrical properties from ion implanted layers. At higher implant anneal temperatures, the SiC surface morphology can seriously degrade as damage-assisted sublimation etching of the SiC surface begins to take place [76]. Because sublimation etching is driven primarily by loss of silicon from the crystal surface, annealing in silicon overpressure can be used to prevent surface degradation during high temperature anneals. Such overpressure can be achieved by close-proximity solid sources, such as using an enclosed SiC crucible with SiC lid and SiC powder near the wafer, or by annealing in a silane-containing atmosphere. T. Ayalew: SiC Semiconductor Devices Technology, Modeling, and Simulation