4.5.3.1 ACCUFET Structure

Figure 4.31: Cross section of an accumulation-channel lateral DMOSFET on SiC sub-insulating substrate.

The principal difference between accumulation-channel lateral DMOSFET shown in Fig. 4.31 and the conventional inversion-layer structure is the presence of a thin n-channel region (accumulation-layer) below the gate oxide using a buried p-well region formed by ion-implantation. The thickness, length, and n-doping concentration of this accumulation-layer are carefully chosen so that it is completely depleted by the built-in potential of the p/n junction. This causes a potential barrier between the n+ source and the n-drift regions resulting in a normally-off device with the entire drain voltage supported by the n-drift region. Thus it can block high forward voltages at zero gate bias with low leakage currents. When a positive gate bias is applied, an accumulation channel of electrons at the SiO$_{2}$-SiC interface is created and hence a low resistance path for the electron current flow from the source to the drain is achieved. This structure offers the possibility of moving the channel away from the oxide interface, thereby removing the consequence of the bad interface quality on the channel mobility. The structure also utilizes the buried p-well region as a shield to high SiC bulk electric field on the gate oxide. T. Ayalew: SiC Semiconductor Devices Technology, Modeling, and Simulation