1.1 Silicon Technology CAD

The well-known Moore's Law [1] states that the number of devices per chip doubles every eighteen months. The expected entitlement of periodic improvements in density and performance has, heretofore, been achieved through evolutionary device scaling and/or increase in chip size. The ever decreasing size of transistors brings up new physical effects of quantitative relevance in short time periods.

Digital integrated circuits contain two basic components: transistors and interconnections. For classical transistor scaling, device performance improves as gate length, gate dielectric thickness, and junction depth are scaled. Some of the main challenges for the fabrication of increasingly scaled devices are related to dopant profiles in shallow junctions and short channels.

Scaled chip wiring (interconnect) suffers from increased resistance due to decrease in conductor cross-sectional area and may also suffer from increased capacitance, if metal height is not reduced with conductor spacing. As operating frequencies continue to spiral upward, parasitic inductive effects must also be considered.

The main reliability issue for thin, tightly spaced interconnect lines of deep-submicron designs is electromigration which can trigger system failure at some undefined future time [2,3].

TCAD (Technology Computer Aided Design) programs for simulating the fabrication process and the electrical behavior of transistors are well accepted in the semiconductor industry [4,5,6]. They present an invaluable help in improving existing technologies and can drastically reduce development time for new emerging technologies and down-scales.