CMOS technologies have witnessed aggressive reduction of the feature size down to the sub 100 nm regime thereby delivering increased performance in terms of higher integration densities, increased speed and lower power consumption. However, further down sizing of the feature size to the deca nanometer regime becomes more challenging with each successive CMOS technology node as fundamental technological and physical limits of existing processes and materials are reached. Key factors that prevent the forever continuous scaling of CMOS devices are [Rairigh05,Brillouët06,Haensch.06]:
Given the restrictions associated with further reductions of the gate length, possible solutions fall into two broad categories: a) introducing structural changes into the transistor, and b) seeking new materials and material modifications. Novel device geometries such as FinFETs, multiple gate MOSFETs and ultra-thin body MOSFETs are promising and could provide the means for continued scaling inline with the ITRS roadmap. Similarly, on the materials side, high-k materials such as Hafnium-based dielectrics [Kirsch06,Chau04] in conjunction with alternative gate materials have shown promising results in demonstrating high performance devices [Majhi06,Chau04], and are considered favorable for scaling. Since the drain current of a MOSFET is proportional to the mobility of the carriers, an alternative choice of improving the device performance while keeping other dimensions constant is through the enhancement of the carrier mobility in the conducting channel. This effect is crucial since the mobility in scaled devices is significantly degraded due to the presence of high vertical fields. In this context, strain engineering has come into limelight as a technique for enhancing the mobility.
Starting with the 90nm technology node, strain engineering has become a critical feature in CMOS technology since it can increase the drain current without reducing the transistor channel length. Furthermore, the technique is compatible with other novel device architectures such as multiple gate or ultra-thin body structures to deliver larger drive currents. However, in order to investigate and design strained Si based device structures, it is necessary to model the carrier mobility in these devices. This thesis is devoted to the study of the effect of strain on the electron mobility. The aim is to develop analytical mobility models by incorporating new physical effects that arise from strain. The models are implemented in a general purpose device simulator, MINIMOS-NT, which is then used to investigate the performance of a novel strain based device structure.
The layout of the thesis is as follows. Chapter 2 gives an overview of the different technologies for introducing strain into the Si channel. A brief chronology of the evolution of strained Si technology is outlined and methods such as substrate-induced strain, local strain and external mechanical strain are described. The effect of strain on the electronic band structure of Si is described in Chapter 3. After reviewing the basic concepts of the theory of elasticity, the strain-induced modifications of conduction and valence bands are discussed for different stress configurations, based on the linear deformation potential theory. The effect of shear stress on the band structure is summarized. Since a consequence of strain is a change in the carrier mobility, it is essential to accurately model the mobility for device simulation purposes. An overview of the different mobility models is presented in Chapter 4. In this section comprehensive models for the low and high field bulk electron mobility in strained Si are derived. Efforts to model the inversion layer mobility are also discussed. Finally in Chapter 5, the analytical models are calibrated against Monte Carlo simulation using analytical and full-band simulations. The path of model implementation into MINIMOS-NT as well as interfacing of the strain distribution from device structure into the device simulator is also outlined. It is then applied to calculate the effective mobility versus the effective field. As an example, a novel device structure, the so called dotFET, is examined using drift-diffusion simulations.