Semiconductor industry has adopted strain engineering for the development of upcoming CMOS technologies for high-speed digital integrated circuits. Strain is introduced as a means to enhance the carrier mobilities in semiconductors. For designing strained Si based device structures, comprehensive models are essential which can estimate the effect of biaxial or uniaxial as well as any other strain configuration on the electron mobility.
This thesis focuses on the effect of strain on electron mobility in Si. Various
mechanisms of generating strain have been reviewed in this work. The goal is to
develop analytical models that describe the electron mobility, taking into
account all the relevant physical modifications that arise due to straining
Si. In particular, band structure calculations indicate a splitting of the
conduction band valleys and, in the presence of shear strain, an additional
deformation of the band minima. A low-field bulk electron mobility model has
been developed for Si under arbitrary stress conditions. The analytical model
includes the effect of strain-induced splitting of the conduction band valleys,
inter-valley scattering, and doping dependence. Inter-valley scattering is
modeled based on the equilibrium electron distribution and the valley splitting
for a given strain tensor. The model is extended to account for the variation
of the effective mass of the 
-valleys with shear strain. The model is
also adapted to obtain the bulk mobilities in strained Ge. The bulk mobility
model for strained Si is coupled together with an existing surface mobility model
for obtaining the inversion layer mobility. The electron transport in strained
Si at high electric-field is investigated using full-band Monte Carlo
simulations. A strain-dependent empirical mobility model has been developed
that describes the velocity components parallel and perpendicular to the
electric field as a function of the strain-induced valley splitting for high
electric field. The high-field model is restricted to such strain conditions
where only one pair of X-valleys is shifted and four valleys remain
degenerate. These conditions include biaxial stress and uniaxial stress applied
along the {100} axes of Si.
The models have been implemented in the general purpose device simulator, MINIMOS-NT. The simulator has been used to perform drift-diffusion based device simulations. A novel device structure comprising of a strained Si bridge grown on a Ge quantum dot is investigated. The so called dotFET structure combines the advantages of strain and SOI technology. An interface was set-up to read in the strain distribution on the dotFET into the device simulator. Simulation results suggest a significant improvement in the linear drain current and a moderate improvement in the saturation current.