These initial simulations of a FEMFET already show effects of the device geometry on the performance, which are related to two-dimensional properties. Fig. 8.19 shows that the charge distribution along the channel in the ON state is far from uniform, which causes strong impact on the ON current. Due to the highly nonlinear properties of a ferroelectric gate dielectric any change of drain or gate voltage shows a strong impact on charge distribution and current. This can be clearly seen in the plotted transfer characteristics (Fig. 8.17, Fig. 8.18), where an increase of the peak voltage by 0.5V leads to a threshold voltage shift of 1.5V. Using the simulator a rigorous analysis of these effects is now possible. The obtained results can be utilized to fulfill several tasks of fundamental interest for device engineering:
The fact that, according to the SIA roadmap [Sem99], the gate length of CMOS is getting shorter and shorter compared to the device size will increase the influence of the drain contact on the potential distribution in the channel, thus increasing the impact of the effects outlined above and, in parallel, the necessity to use a rigorous analysis tool as it is presented in this thesis.