8.3 Analysis of a Ferroelectric Memory Field Effect Transistor

As outlined in Section 7.2, the FEMFET is one of the most attractive designs of ferroelectric non-volatile memory cells, especially because of its low space consumption. However this compact design also increases the complexity of and accordingly the demands on a simulation tool.

The insertion of a material with a high permittivity has strong impact on the device performance. This became one of the key issues of device design and is being investigated heavily, with respect to material issues [LWK+98][MOS+99] and the performance point of view [CCR+99][CCV+99][IRCW99][KYY+98][YKL98].

The modification of the dielectric properties of the gate insulator has visible consequences for device performance. Similarly to regular CMOS devices an increase of the relative dielectric constant $\epsilon_r$ shifts the

characteristics to the right. This can be avoided by an increase of the oxide thickness which has in turn a significant impact on the electrical behavior of the device. Since the distance from the gate to the channel is larger, this leads to a loss of control over the channel. The most serious consequence of this effect is a significant increase of the drain current in the OFF state of the transistor.

Next will be demonstrated that the simulation tool can keep up with the demands of TCAD by extraction of the significant device information like transfer characteristics, field distribution, and space charge density.

For the simulation an NMOS with $1{\mu}\mathrm{m}$ gate length was transformed into a FEMFET, by entering a ferroelectric segment under the gate. In order to keep parasitic effects between gate and drain/source and between drain/source and channel low, two non-ferroelectric spacers are placed on both sides of the gate. The geometry of the simulated device is outlined in Fig. 8.14. Acceptor- and Donor doping distribution are shown in Fig. 8.15 and Fig. 8.16, respectively.

**Figure 8.14:** Geometry of the gate area
$\resizebox{10cm}{!}{ \psfrag{Gate}{Gate} \psfrag{Drain}{Drain} \psfrag{Source}{S... ...ric}{Ferroelectric Material} \includegraphics[width=10cm]{femfet/geometry.eps} }$

**Figure 8.15:** Acceptor doping distribution of NMOS and FEMFET
$\resizebox{11cm}{!}{ \includegraphics[width=11cm]{acceptor_img.eps} }$

**Figure 8.16:** Donor doping distribution of NMOS and FEMFET
$\resizebox{11cm}{!}{ \includegraphics[width=11cm]{donor_img.eps} }$

The operating conditions for the transistor were chosen at values similar to those of a CMOS transistor of the same gate length. $V_\mathrm{D}$ was $1.0\mathrm {V}$ , bulk and source bias $V_\mathrm{B}=V_\mathrm{S}=0$ , respectively.