7.2 The Ferroelectric Memory Field Effect Transistor

The Ferroelectric Memory Field Effect Transistor (FEMFET) takes direct advantage of the hysteretic properties of polarization and displacement of a ferroelectric material. The FEMFET is constructed by inserting a ferroelectric segment into the sub-gate area of an NMOS, as outlined in Fig. 7.9.

Figure 7.9: Ferroelectric non-volatile memory field effect transistor

This device design is attractive for large scale integration, as it represents a very compact design of a complete non-volatile memory cell. The achievable integration density is identical to the well-known floating-gate Flash memory cells, but the operating conditions are much smoother, as the information can be stored with the default operating voltages in the range of $1$ V and, same as for the transistor-capacitor designs, no higher voltage peaks, as necessary for the floating gate device, are required.

This design was introduced by Miller and McWorther in 1992 [MM92], and a compact model for this device was extracted. In 1999 an advanced compact model introducing the Preisach hysteresis was presented by Ullmann et al. [UGH+99]. As a rigorous analysis shows, these compact models by far underestimate the complexity of the properties of the device.

Processing this device proved to be very complicated, especially the interface between substrate surface and ferroelectric layer caused many problems. Recently these problems seem to have been solved and the first prototypes have been presented [MWC99].