7.1.2 Single Cell Design

In order to achieve higher integration densities single-transistor single-capacitor structures have become the state-of-the-art design for ferroelectric memories.

Figure 7.5: 1C1T circuit

The equivalent circuit is plotted in Fig. 7.5. The operating principle is based on moving the charge between the bit line capacitor $C_\mathrm{B}$ and the ferroelectric capacitor $C_F$. The drawback of this method is that an external reference voltage has to be generated in order to allow the evaluation of the memory state.

During write operation, the memory cell is accessed by raising the wordline (WL) voltage, which turns the access transistor in ON state, and at the same time pushes the ferroelectric capacitor into negative saturation, no matter whether the cell was in the ``1'' or ``0'' state. In the second half of the write cycle, the plateline (PL) voltage is raised. As the transistor is in the ON state, the potential difference between bitline (BL) and plateline modifies the operating point of the capacitor. In case of ``0'', the bitline is not raised and $C_\mathrm{F}$ will be in positive saturation, and after the write cycle is finished, $C_\mathrm{F}$ will be defined by the positive remanent polarization $P_\mathrm{Rem}$. If the bitline is raised and a ``1'' is written, the potential difference will be insignificantly low and $C_\mathrm{F}$ will be at the negative remanent polarization $-P_\mathrm{Rem}$, and remain there after the write cycle.

Figure 7.6: Sensing scheme of the write operation of the 1C1T circuit

Figure 7.7: Approximation of the hysteresis loop with capacitors

Figure 7.8: Timing diagram of the read operation of the 1C1T circuit

Fig. 7.8 shows the timing diagram of the read cycle. At first the bitline is actively set to 0V. After the bitline capacitor is discharged, writeline and plateline are activated using the supply voltage $V_{DD}$. Now $C_F$ and $C_B$ form a capacitive voltage divider between plateline and ground. Depending on the information in the memory cell, the operating points of the ferroelectric material differ, and so does the capacity of $C_F$. If the ferroelectric hysteresis is approximated by two different capacitors (Fig. 7.7), the bitline voltage reads as

$$V_0= \frac{C_0}{C_0+C_B}V_{DD}$$ (7.1)

if the stored information is ``0'' and

$$V_1= \frac{C_1}{C_0+C_B}V_{DD}$$ (7.2)

if the stored information is ``1''. These two different voltages are detected by the sense amplifier, and, similarly to the 2C2T structure, the original information is restored in the memory cell.