7.1.1 Double Cell Design

The double cell (2C2T) structure which is outlined in Fig. 7.3 was introduced by Evans and Womack in 1988 already [EW88]. For write operation the bit line (BL) and the inverse bit line ( $\overline\mathrm{BL}$) are set to the wanted states ( $V_\mathrm{sup}$ for logical ``1'' and ground for logical ``0'') by the sense amplifier. Plate line and word line have to be activated simultaneously. Depending on the branch of the double structure two different operating points will evolve at the capacitors. Due to the ferroelectric properties the charge difference which represents different polarizations in the materials, will remain at this level even when the sense amplifier is turned off after write operation.

During read operation the charge at the two bit lines will differ, and accordingly a potential will occur at the two entries of the sense amplifier. The amplifier itself will drive the potential back to the initial write potential, thus restoring the original state immediately after a write operation [JCJ+97]. The timing diagram of read and write operations is given in Fig. 7.4.

Figure 7.3: 2C2T circuit

Figure 7.4: Sense scheme of a 2C2T circuit