5. Dielectric Degradation and Failure Mechanisms

ONE elementary aspect of semiconductor devices is their reliable performance for a determined period of time. There are many extrinsic and intrinsic degradation mechanisms which can lead to device and circuit failure. Due to aggressive scaling of device geometries, increasing electric fields across the device, and the utilization of new materials many degradation mechanisms which were formerly of minor importance can now lead to severe reliability concerns.

In this chapter a range of degradation mechanisms affecting the gate dielectric is described and their implication on device failure is discussed. Special focus is put upon mechanisms concerning the silicon/silicon-dioxide interface as its properties play a very important role for negative bias temperature instability. The effect of trap-assisted tunneling and its implication on the threshold voltage due to trapped carriers, similar to charge trapping in NBTI (Section 6.6), are examined in detail.