In this work, the design and implementation of the data level of the Viennese Integrated System for TCAD Applications (VISTA) [Selb91] is presented. In Chapter 2 the tasks and corresponding data occurring in a TCAD framework are analyzed. The data flow of conventional and framework-compliant TCAD tools is analyzed, and concepts for integrating these tools into the framework are presented. Representational aspects of tool and framework data are discussed, and features, that a data level must exhibit are identified.
Chapter 3 presents some concepts for data level architectures and illustrates them with existing approaches implementing these concepts. The VISTA data level approach is introduced and compared to existing data levels.
Chapter 4 discusses the VISTA data level architecture and its design guidelines. The PIF interchange format is presented in both its ASCII and binary representations, and compared to other popular interchange formats.
Chapter 5 clarifies how the data level implementation was carried out from the software engineering viewpoint through the use of automated code generation tools allowing programming in high-level concepts.
In Chapter 6 the VISTA data level implementation is discussed in detail. The layered structure of the procedural interface is explained, and semantic and performance issues are discussed.
High-level libraries are discussed in Chapter 7, their importance is underlined and the GRS grid support library is presented in detail. The application of the VISTA object oriented programming system VOOPS on this library is shown, and the KIRKPATRICK method [Kirk83] for point location, employed by this library to speed up interpolation on unstructured grids, is analyzed.
Chapter 8 presents the capacitance simulator VLSICAP which is integrated on the data and task level into VISTA. The integration guidelines are derived from the simulator architecture, and the chosen method of integration is motivated. Two industrial problems are investigated with VISTA and VLSICAP: a microstrip line, where the design goal is to minimize capacitive cross-talk between the microstrip and adjacent lines, and a parasitic MOSFET situated at the isolating oxide, where the goal is to find the gate-bulk capacitance characteristic in order to get an estimation for the threshold voltage.
Conclusions are drawn in Chapter 9, and an outlook on future directions for data level development is presented.