4.2.1 Technology Background

During the previous two decades, the memory demand increased significantly. The response from the scientific community was to produce memory technology scaling by 19 generations in the last 24 years and in the process out-pacing even Moore's Law [72]. The technology node scaling over the past several years is depicted in Figure 4.6.

Figure 4.6: Technology scaling for FLASH memory.

Masouka [145] proposed the first FLASH EEPROM, which reduced the cost of the memory array compared to that of previously-used EEPROM memories and was based on a NOR cell. A few years later, Masouka also proposed a NAND gate based FLASH EEPROM [146] which is a floating gate cell whose efficiency was far superior to that of a NOR cell. However, because of the serial architecture of the NAND cell, its read access was slow. Over the years the NAND cell has been shown as down-scalable far more than the NOR cell, down to the 15nm node. However, due to concerns regarding lithographic limitations, coupling ratio, and crosstalk interference, it is suggested that the NAND cell will not be scalable far below the 15nm node [232]. Others propose charge trapping devices which are capable of scaling the Floating Gate NAND cell beyond 15nm, but below $\sim$10nm, both charge trapping and Floating Gate devices have too few electrons for robust storage [130]. In order to find alternatives to the standard two-dimensional cell flash, research was directed towards three-dimensional structures [101], [115]. These structures do not rely on charge storage and are thereby naturally not limited by the available number of electrons.

Some three-dimensional memory structures proposed in the past 5 years include the Terabit Cell Array Transistor (TCAT) structure from Jang et al. [94], the 3D Dual Control-gate with Surrounding Floating-gate (DCSF) from Whang et al. [225], the Vertical Stacked Array Transistor (VSAT) [100] from Kim et al., the Vertical-gate NAND [102] from Kim et al., and the BiCS [206] structure proposed by Tanaka. One similarity between all three-dimensional structures is the use of a polysilicon active layer and deposited tunnel oxide.

Figure 4.7: Image of a typical BiCS structure with memory holes.

The latest BiCS structure proposed by Katsumata et al. [97] is the Pipe-shaped BiCS (P-BiCS) and is meant to achieve a highly reliable memory film, whose read and write operations are governed by FN tunneling. Figure 4.7 shows a typical P-BiCS structure with only four Si-SiO$_2$ layers depicted. In order for the cost reduction to be significant, a 16-layer Si-SiO$_2$ structure is the minimum requirement [148]. The fabrication steps of such a complex structure are surprisingly simple and are described in [97]:

1. Formation of the bottom pipe connection.
2. Deposition of a sacrificial film and subsequent memory hole formation.
3. Deposition of a sacrificial film and subsequent select-gate electrode deposition.
4. Formation of the select-gate hole.
5. Removal of the sacrificial film.
6. Deposition of the memory film,
7. Deposition of the body silicon film.

For etching of the memory hole (Step 2), the entire 16-layered structure consisting of interchanging silicon and silicon dioxide layers must be etched through for a hole approximately 50nm wide. The silicon layers must be etched using an etchant to which silicon dioxide is etch-resistant and vice versa. This way, the silicon layer serves as a mask and etch block during silicon dioxide etching and silicon dioxide serves as a mask and etch block during silicon etching. For the etching of both materials, an anisotropic etch process is preferred with flat, vertical sidewalls. Therefore, wet chemical etching is undesirable since it produces angled sidewalls which are bulk silicon orientation-dependent. Highly selective reactive ion etching could be possible, but the hole depth required and potential damage to the highly-sensitive material surfaces rules out this possibility. The best method appears to be a highly selective and anisotropic ion enhanced plasma etching process.