Abstract

MICROELECTRONICS has reached a point where quantum effects have a major impact on the electrical characteristics of semiconductor devices. One of the most important effects in this regime is the quantum-mechanical tunneling of carriers through thin dielectric layers. On the one hand, this leads to increased power consumption and thus limits the thickness of the gate dielectric. On the other hand, tunneling effects are used in non-volatile memory devices to transfer charge to an isolated floating gate.

The tunneling current is caused by the transition of carriers from one electrode through a classically isolating region to another electrode. Three major factors influence this process: the carrier energy distribution at both electrodes, the quantum-mechanical transmission coefficient of the energy barrier between the electrodes, and the presence of traps in the insulating layer which may assist in the tunneling process.

The carrier energy distribution is of major importance for the tunneling process. The FERMI-DIRAC or MAXWELL-BOLTZMANN distribution is frequently used to approximate this distribution. These expressions are, however, only valid near equilibrium and fail to describe the distribution of hot carriers. In this work an alternative expression for the distribution function, which is based on the carrier concentration, temperature, and kurtosis, was applied. This distribution shows good agreement with results from simulations and accurately reproduces the high-energy tail of the distribution. The heated MAXWELLian distribution, which only accounts for the electron concentration and temperature, completely fails to reproduce the high-energy tail and highly overestimates the tunneling current density.

The quantum-mechanical transmission coefficient is calculated by solving the stationary SCHRÖDINGER equation in the region considered for tunneling. The coefficient depends on the shape of the energy barrier in the dielectric layer. Dielectrics which consist of a single layer give rise to a linear potential variation in the barrier, yielding either a trapezoidal or a triangular band diagram. Analytical models can be derived to approximately calculate the transmission coefficient in these cases, based on the WENTZEL-KRAMERS-BRILLOUIN approximation or on GUNDLACH's formula.

With reduced device dimensions, however, the gate dielectric in MOS devices must be scaled accordingly which, for the commonly used material SiO$_2$, leads to an intolerably high gate current density. To overcome this problem, gate dielectric stacks including high-$\kappa$ dielectrics have been proposed.

In such dielectric stacks the band profile has a non-linear shape, and models based on triangular or trapezoidal barriers are no more valid. Instead, SCHRÖDINGER's equation must be solved using the transfer-matrix or the quantum transmitting boundary method. These methods have been studied and the quantum transmitting boundary method was found superior due to its better numerical stability and the possibility to apply it to two- and three-dimensional problems.

Non-volatile memory devices need to endure up to $10^5$ write and erase cycles at a voltage of 8-12V. This repeated high-field stress introduces defects in the tunneling dielectric, which give rise to trap-assisted tunneling current at low electric fields. That trap generation is considered a major reason for device degradation. In this work trap-assisted tunneling is modeled as a two-step process during which energy relaxation by phonon emission takes place. The trap occupancy in the dielectric is described by a time-dependent rate equation. To solve this equation, an iterative procedure is applied.

Models to describe the outlined processes have been implemented into the general-purpose device simulator MINIMOS-NT. Several applications are investigated, where a distinction between MOS transistors and non-volatile memory devices is made. The applicability of alternative dielectric materials is investigated and, as an example, a MOS capacitor with a ZrO$_2$ dielectric is simulated and compared with measurements. Non-volatile memory devices such as conventional EEPROM devices, trap-rich dielectric devices, multi-barrier tunneling devices, and devices which use layered tunnel barriers to improve the retention time are investigated. With the implemented models, MINIMOS-NT can be used for the evaluation of tunneling currents in device structures of arbitrary complexity.

A. Gehring: Simulation of Tunneling in Semiconductor Devices