5.1.1 Tunneling Paths in MOS Transistors

Tunneling in an MOS transistor, as shown in the left part of Fig. 5.1, basically can be separated into a path between the gate and the channel, and a path between the gate and the the source and drain extension areas [249]. Tunneling in the source and drain extension areas can exceed tunneling in the channel by orders of magnitude. This is related to two effects: First, instead of n-p or p-n tunneling, n-n or p-p tunneling prevails. Second, the potential difference and thus the bending of the energy barrier is high. This increased tunneling current in the source and drain extension areas can be a serious problem if measurements are performed on long-channel MOSFETs to characterize their short-channel pendants, because the edge tunneling currents exceed the channel tunneling current by orders of magnitude. Furthermore, there is a fundamental difference between tunneling in MOS transistors and MOS capacitors [250,96]. In contrast to MOS transistors, MOS capacitors which are biased in strong inversion cannot supply the amount of carriers as predicted by the tunneling model. This effect is termed substrate-limited tunneling, because the tunneling current is limited by the generation rate in the substrate. In the channel of an inverted MOS transistor, on the other hand, carriers can always be supplied by the source and drain contacts. This effect is depicted in the right part of Fig. 5.1.

Figure 5.1: The different tunneling paths (channel tunneling, source and drain extension tunneling) in an MOS transistor (left). In an MOS transistor biased in inversion (right), tunneling electrons are supplied from the source and drain reservoirs, which is not possible in an MOS capacitor.

A. Gehring: Simulation of Tunneling in Semiconductor Devices