6.3.3 CMOS Inverter

The schematic of a CMOS inverter is shown in Fig. 6.15. The evolution of the node voltages during DC operating point calculation is shown in Fig. 6.16. Best results were obtained with $\kappa$ = 1. With ABC 21 iterations were needed whereas with DBC 25 iterations were needed.

For ABC one gets K^A = 21/24 = 0.875 and for DBC K^D = 25/27 = 0.926, both values being even better than the ``ideal'' simulation. Again, as for the CML inverter, each point of the DC transfer characteristic required the same number of iterations for both boundary conditions (7-17).

For this simple circuit convergence can be obtained without any G_S at a convergence rate similar to k₀.

Figure 6.15: CMOS inverter.

Figure 6.16: Evolution of the node voltages during DC operating point calculation for the CMOS inverter with $\kappa$ = 1.

Figure 6.17: Simulated DC transfer characteristic for the CMOS inverter.