A. Thermal Equivalents

Figure A.1: a) Geometry and b) temperature distribution of a material block.

Solving the one-dimensional static lattice heat flow equation

$$\rho_{L}^{} {\frac{\partial T_{L}}{\partial t}}$$ div S_L = (A1)

$$\kappa_{L}^{}$$ S_L = (A2)

one can derive a thermal equivalent model for a device with a geometry as shown in Fig. A.1a. With the boundary conditions T_L(- a) = T₁ and T_L(a) = T₂ and under the assumption of constant heat generation H the solution for the lattice temperature inside the device reads

$${\frac{P_{E}}{8 \cdot G_{\mathit{th}}}} \left(\vphantom{1 - \left(\frac{x}{a}\right)^2 }\right. \left(\vphantom{\frac{x}{a}}\right. {\frac{x}{a}} \left.\vphantom{\frac{x}{a}}\right)^{2}_{} \left.\vphantom{1 - \left(\frac{x}{a}\right)^2 }\right) {\frac{\Delta T}{2}} {\frac{x}{a}} \overline{T}$$ (A3)

with

$$\Delta \overline{T} {\frac{T_{1} + T_{2}}{2}}$$ = T₁ - T₂, (A4)

$${\frac{\kappa_{L} \cdot A}{2 \cdot a}}$$ P_E = H ^. A ^. 2 ^. a,         G_th (A5)

It consists of a linear term arising from the boundary condition and a quadratic term arising from heat generation inside the device due to the dissipated electrical power P_E. The temperature distribution is shown in Fig. A.1b.

To derive a thermal equivalent circuit the discretized lattice heat flow equation as solved by MINIMOS-NT can be used. Assuming constant electrical power dissipation P_E and a constant thermal heat capacity c_L the expression for a grid point i reads [36]

$$\sum_{j}^{} \sum_{j}^{} {\frac{P_{E}}{2}} {\frac{T_{L} - T_{L,o}}{\Delta t}}$$ = (A6)

$$\left(\vphantom{ T_{i} - T_{j} }\right. \left.\vphantom{ T_{i} - T_{j} }\right)$$ P_{i, j} = (A7)

$$\rho_{L}^{}$$ C_th = (A8)

The sum in (A.6) considers the contribution of all neighbor points j with P_{i, j} being the thermal heat flowing from point i to point j. Using heat flows instead of electrical currents and temperatures instead of voltages an electrical equivalent circuit can be used to model (A.6). This equivalent circuit is shown in Fig. A.2 for grid point i in a two-dimensional situation with four neighbor points.

Figure A.2: a) Grid point i and 4 neighbors used for the discretization of the lattice heat flow equation. b) Electrical analog circuit for the lattice heat flow equation.

This equivalent circuit is approximately valid for the most general case. The geometry of a schematic layout is shown in Fig. A.3. To keep the problem tractable, device simulation is normally restricted to the electrical active regions which make up only a small portion of the chip. Heat generation is even further restricted to small areas of the device which normally are the space charge regions for bipolar devices and the channel regions for MOS devices. For other areas like buried collectors and substrates heat generation is normally negligible as either the electric field, the current density, or both are low. Therefore the heat generation term H can be neglected for these areas and the thermal equivalent circuit reduces to resistances and capacitances.

On the other hand, for the electrical active region the thermal resistances and capacitances are of minor importance due to their small size. This is the reason why power dissipation in electrical devices is normally modeled by a power source alone which can be considered as reducing the power source to a point source.

It is worthwhile to point out the simplifying assumptions made in the derivations above:

• A constant thermal conductivity $\kappa_{L}^{}$ has been assumed which is a very crude approximation. Using the exponential expression from [56]

  $$\kappa_{L}^{} {\frac{\mathrm{W}}{\mathrm{K\ cm}}} \left(\vphantom{\frac{T}{300\ K}}\right. {\frac{T}{300\ K}} \left.\vphantom{\frac{T}{300\ K}}\right)^{-4/3}_{}$$ (A9)

  
  
  gives and error in the solution of the linear heat diffusion equation in the order of 30 % [8].
• Heat generation has been assumed constant inside the device. This gives a good approximation only when the temperature rise due to H is small compared to the temperature rise induced by the boundary condition.

Figure A.3: Electrical and thermal modeling of several transistors.