Surface-Channel Versus Buried-Channel Devices
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Buried-channel devices exhibit a higher minority carrier low-field
mobility than the surface-channel devices due to less surface scattering.
Is seems that they show advantages over the surface-channel devices in
the reliability issue [468][323][312]. The Buried-channel
design has, however, some drawbacks comparing with the surface-channel design:
- The current path is moved away from the interface, which reduces the
device transconductance
[514]. This effect can compensate the benefit from a higher
minority-carrier mobility [361].
- The two-dimensional (2D) effects, like the
drain-induced barrier lowering, the threshold voltage roll-off with
decreasing channel length and the punch-through are more pronounced in the
buried-channel devices [514][361]. Since the supply voltage
is reduced for submicrometer CMOS circuits, there is a demand for devices
with a low threshold voltage. The surface-channel devices obey much better
turn-off characteristics than devices with a buried channel, that means,
they should be used in the deep submicrometer CMOS circuits. Recently,
however, -buried-channel MOSFETs with gates in the
quarter- range with quite small 2D effects have been
designed [351][301]. The key issue in achieving this goal
was the application of very shallow source/drain junctions.
- Buried-channel devices exhibit an anomalous subthreshold behavior at low
temperatures (e.g. ). This poor turn-off characteristic is
produced by the re-ionization of the compensating shallow implant by
reducing the gate bias, which leads to a lower decrease of the amount
of channel charge in the subthreshold region compared to the
surface-channel devices [139]. It is established in the
literature that devices for cryo-temperature applications must be of
surface-channel type [141]. Recently experiments have shown
that the ionization of dopants takes place in the buried-channel devices
at liquid-nitrogen temperature for short channel lengths and not too low
drain voltages (at sufficiently large lateral fields), thus avoiding the
freeze-out problems [142]. The effect has been explained
by the ionization barrier lowering due to the Poole-Frenkel effect.
Note that -buried-channel MOSFETs exhibit less two-dimensional effects than
their -buried-channel counterparts. Therefore -gate CMOS technology
seems to be more scalable than CMOS technology [363].
Next: 2.1.1 Advanced Gate Design
Up: 2.1 Dual Gate CMOS
Previous: 2.1 Dual Gate CMOS
Martin Stiftinger
Sat Oct 15 22:05:10 MET 1994