References

1

ABBAS, S. A., AND DOCKERTY, R. C. Hot-carrier instability in IGFET's. Appl. Phys.Lett. 27, 3 (1975), 147-148.

2

ABDURAKHMANOV, K. P., MIRAKHMEDOV, S., AND TESHABAEV, A. T. Characteristics of the distribution of the density of states in heavily doped silicon. Sov.Phys.Semicond. 12, 4 (1978), 457-459.

3

ABRAMOWITZ, M., AND STEGUN, I. A. Handbook of Mathematical Functions. Dover Publications, Inc., New York, 1970.

4

ACOVIC, A., DUTOIT, M., AND ILEGEMS, M. Characterization of Hot-Electron-Stressed MOSFET's by Low-Temperature Measurements of the Drain Tunnel Current. IEEE Trans.Electron Devices 37, 6 (1979), 1467-1476.

5

ACOVIC, A., HSU, C. C.-H., HSIA, L.-C., BALASINSKI, A., AND MA, T.-P. Effects of X-Ray Irradiation on GIDL in MOSFET's. IEEE Electron Device Lett. 13, 4 (1992), 189-191.

6

ADA-HANIFI, M., SICART, J., ROBERT, J. L., AND BIELLE-DASPET, D. Hubbard's sub-band conduction in Si poly-SiO transition layers. Solid-State Electronics 30, 7 (1987), 765-769.

7

ADAR, R. Spatial Integration of Direct Band-to-Band Tunneling Currents in General Device Structures. IEEE Trans.Electron Devices 39, 4 (1992), 976-981.

8

AHN, S. T., HAYASHIDA, S., IGUCHI, K., TAKAGI, J., WATANABE, T., AND SAKIYAMA, K. Hot-Carrier Degradation of Single-Drain PMOSFET's with Differing Sidewall Spacer Thicknesses. IEEE Electron Device Lett. 13, 4 (1992), 211-213.

9

ANCONA, M. G., SAKS, N. S., AND MCCARTHY, D. Lateral Distribution of Hot-Carrier-Induced Interface Traps in MOSFET's. IEEE Trans.Electron Devices ED-35, 12 (1988), 2221-2228.

10

ANCONA, M. G., AND SAKS, N. S. Simulation of hot-carrier degraded MOSFETs. In Proc: NASECODE VI (Dublin (Ireland), 1989), pp. 415-421.

11

ANCONA, M. G., AND SAKS, N. S. Numerical simulation of 3-level charge pumping. J.Appl.Phys. (1992). (accepted)

12

ANDO, T., FOWLER, A. B., AND STERN, F. Electronic properties of two-dimensional systems. Rev.Modern Physics 54, 2 (1982), 437-672.

13

ARGYRES, P. N. Theory of Tunneling and its Dependence on Longitudinal Magnetic Field. Physical Review 126, 4 (1962), 1386-1393.

14

ARNOLD, E. Conduction mechanisms in bandtails at the Si-SiO interface. Surface Science 58 (1976), 60-70.

15

ASENOV, A., BERGER, J., SPECKBACHER, P., KOCH, F., AND WEBER, W. Spatially-resolved measurements of hot-carrier generated defects at the Si-SiO interface. In Proc: Int.Conf. on Insulating Films on Semicond. (INFOS) (Liverpool (U.K.), 1991), pp. 247-250.

16

ASENOV, A., BERGER, J., WEBER, W., BOLLU, M., AND KOCH, F. Hot-carrier degradation monitoring in LDD n-MOSFETs using drain gated-diode measurements. In Proc: ESSDERC (Montreux (Swiss), 1991), Elsevier, pp. 445-448.

17

ATALLA, M. M., TANNEBAUM, E., AND SCHEIBNER, E. J. Stabilization of Silicon Surfaces by Thermally Grown Oxides. Bell Syst.Tech.J. 38 (1959), 749-783.

18

AYMERICH-HUMET, X., SERRA-MESTRES, F., AND MILLÁN, J. An analytical approximation for the Fermi-Dirac integral . Solid-State Electronics 24, 10 (1981), 981-982.

19

AYRES, J. R. Current DLTS Measurements on Poly-Si Thin Film Transistors. In Proc: ESSDERC (Leuven (Belgium), 1992), Elsevier, pp. 468-479.

20

BACCARANI, G., WORDEMAN, M., AND DENNARD, R. Generalized Scaling Theory and Its Application to a 1/4 Micrometer MOSFET Design. IEEE Trans.Electron Devices ED-31, 4 (1984), 452-462.

21

BACCARANI, G., GNUDI, A., AND VENTURA, D. Hot-electron investigation in semiconductor devices using a multidimensional spherical harmonics expansion of the Boltzmann transport equation. In Proc: Int. Workshop on Computational Electronics (Urbana-Champaign (Illinois), 1992), pp. 19-24.

22

BAKER, F. K., PFIESTER, J. R., MELE, T. C., TSENG, H.-H., TOBIN, P. J., HAYDEN, J. D., GUNDERSON, C. D., AND PARRILLO, L. C. The Influence of Fluorine on Threshold Voltage Instabilities in P Polysilicon Gated P-Channel MOSFETs. In Proc: Int.Electron Devices Meeting (1989), pp. 443-446.

23

BAKKER, J. G. C. Simple Analytical Expression for the Fringing Field and Fringing-Field-Induced Transfer Time in Charge-Coupled Devices. IEEE Trans.Electron Devices 38, 5 (1991), 1152-1161.

24

BALASINSKI, A., CHEN, W., AND MA, T.-P. Effects of Combined X-ray Irradiation and Hot-Electron Injection on NMOS Transistors. J.Electronic Materials 21, 7 (1992), 737-743.

25

BANERJEE, S., RICHARDSON, W., COLEMAN, J., AND CHATTERJEE, A. A New Three-Terminal Tunnel Device. IEEE Electron Device Lett. EDL-8, 8 (1987), 347-349.

26

BANERJEE, S., COLEMAN, D., RICHARDSON, W., AND SHAH, A. Leakage Mechanisms in the Trench Transistor DRAM Cell. IEEE Trans.Electron Devices ED-35, 1 (1988), 108-116.

27

BANGHART, E. K., LAVINE, J. P., TRABKA, E. A., NELSON, E. T., AND BURKEY, B. C. A Model for Charge Transfer in Buried-Channel Charge-Coupled Devices at Low Temperatures. IEEE Trans.Electron Devices 38, 5 (1991), 1162-1174.

28

BATRA, S., PARK, K., LIN, J., YOGANATHAN, S., LEE, J. C., BANERJEE, S. K., SUN, S. W., AND LUX, G. Effect of Dopant Redistribution, Segregation, and Carrier Trapping in As-Implanted MOS Gates. IEEE Trans.Electron Devices 37, 11 (1990), 2322-2330.

29

BELLENS, R., HEREMANS, P., GROESENEKEN, G., AND MAES, H. E. Characterization and analysis of hot-carrier degradation in p-channel transistors using constant current stress experiment. In Proc: ESSDERC (Bologna (Italy), 1987), pp. 159-162.

30

BELLENS, R., GROESENEKEN, G., HEREMANS, P., AND MAES, H. E. On the different time dependence of interface trap generation and charge trapping during hot carrier degradation in CMOS. In Proc: ESSDERC (Leuven (Belgium), 1992), Elsevier, pp. 465-468.

31

BERGLUND, C. N., AND POWELL, R. J. Photoinjection into SiO: Electron Scattering in the Image Force Potential Well. J.Appl.Phys. 42, 2 (1971), 573-579.

32

BERGNER, W., AND KIRCHER, R. Modeling of Band-to-Band Tunneling Mechanisms. In Proc: Int.Conf. on Solid-State Devices and Materials (Sendai (Japan), 1990), pp. 135-137.

33

BERGONZONI, C., AND DOYLE, B. Simulations of aging effects in MOS transistors. In Proc: ESSDERC (Bologna (Italy), 1987), pp. 721-724.

34

BERGONZONI, C., AND LIBERA, G. D. Physical Characterization of Hot-Electron-Induced MOSFET Degradation Through an Improved Approach to the Charge-Pumping Technique. IEEE Trans.Electron Devices 39, 8 (1992), 1895-1901.

35

BLAKEMORE, J. S. Approximations for Fermi-Dirac integrals, especially the function used to describe electron density in a semiconductor. Solid-State Electronics 25, 11 (1982), 1067-1076.

36

BOLLU, M., KOCH, F., MADENACH, A., AND SCHOLZ, J. Electrical switching and noise spectrum of Si-SiO interface defects generated by hot electrons. Appl.Surf.Science 30 (1987), 142-147.

37

BONCH-BRUEVICH, V. L. On the theory of heavily doped semiconductors. Soviet Physics-Solid State 4, 10 (1963), 1953-1962.

38

BORCHERT, B., HOFMANN, K. R., AND DORDA, G. Positive and Negative Charge Generation by Hot Carriers in n-MOSFETs. Electron.Lett. 19, 18 (1983), 746-747.

39

BRAVAIX, A., AND VUILLAUME, D. A simple charge-pumping method to measure the logarithmic-time dependence of trapped oxide charge in P-MOSFET's. In Proc: ESSDERC (Leuven (Belgium), 1992), Elsevier, pp. 469-472.

40

BREWS, J. Theory of carrier-density fluctuations in an IGFET near threshold. J.Appl.Phys. 46 (1975), 2181-2192.

41

BREWS, J. A charge-sheet model of the MOSFET. Solid-State Electronics 21 (1978), 345-355.

42

BROX, M., WOHLRAB, E., AND WEBER, W. A physical lifetime prediction method for hot-carrier-stressed P-MOS transistors. In Proc: Int.Electron Devices Meeting (1991), pp. 525-528.

43

BRUGLER, J. S., AND JESPERS, P. G. A. Charge Pumping in MOS Devices. IEEE Trans.Electron Devices ED-16, 3 (1969), 297-302.

44

BULUCEA, C., RUSU, A., AND POSTOLACHE, C. Surface breakdown in silicon planar junctions-A computer-aided experimental determination of the critical field. Solid-State Electronics 17, 9 (1974), 881-888.

45

BULUCEA, C. Avalanche injection into the oxide in silicon gate-controlled devices-I. Theory. Solid-State Electronics 18 (1975), 363-374.

46

BULUCEA, C. Avalanche injection into the oxide in silicon gate-controlled devices-II. Experimental results. Solid-State Electronics 18 (1975), 381-391.

47

CARNES, J. E., KOSONOCKY, W. F., AND RAMBERG, E. G. Free Charge Transfer in Charge-Coupled Devices. IEEE Trans.Electron Devices ED-19, 6 (1972), 798-808.

48

CASTAGNE', R., AND VAPAILLE, A. Description of the SiO-Si interface properties by means of very low frequency MOS capacitance measurements. Surface Science 28 (1971), 157-193.

49

CILINGIROGLU, U. A general model for interface-trap charge-pumping effects in MOS devices. Solid-State Electronics 28, 11 (1985), 1127-1141.

50

CILINGIROGLU, U. A Two-Device Bistable Memory Circuit Without Feedback Loop. IEEE J.Solid-State Circuits SC-17, 3 (1982), 593-596.

51

CILINGIROGLU, U. A Pulsed Interface-Probing Technique for MOS Interface Characterization at Mid-Gap Levels. IEEE Trans.Electron Devices 35, 12 (1988), 2391-2396.

52

CILINGIROGLU, U. Charge-Pumping Spectroscopy with Pulsed Interface Probing. IEEE Trans.Electron Devices 37, 1 (1990), 267-272.

53

CILINGIROGLU, U. Bistable Storage in Pulsed Gate-Controlled Diodes. IEEE Electron Device Lett. 12, 6 (1991), 338-340.

54

CHAKRABORTY, P. K., AND BISWAS, J. C. Theory of interband tunneling in semiconductors. Solid-State Electronics 28, 5 (1985), 493-497.

55

CHAKRABORTY, P. K. A study of the effect of interband tunneling current on the product of HgCdTe photodiodes. Solid-State Electronics 34, 6 (1991), 665-666.

56

CHAKRABORTY, P. K. A Study of Interband Tunneling Under Nonuniform Electric Field. IEEE Trans.Electron Devices 40, 1 (1993), 214-219.

57

CHAN, T. Y., CHEN, J., KO, P. K., AND HU, C. The Impact of Gate-Induced Drain Leakage Current on MOSFET Scaling. In Proc: Int.Electron Devices Meeting (1987), pp. 718-721.

58

CHANG, C., AND LIEN, J. Corner-field induced drain leakage in thin oxide MOSFET. In Proc: Int.Electron Devices Meeting (1987), pp. 714-717.

59

CHANG, J., HADDAD, S., SWAMINATHAN, B., AND LIEN, J. Drain-Avalanche and Hole-Trapping Induced Gate Leakage in Thin-Oxide MOS Devices. IEEE Electron Device Lett. 9, 11 (1988), 588-590.

60

CHAPMAN, R. A., WEI, C. C., BELL, D. A., AUR, S., BROWN, G. A., AND HAKEN, R. A. 0.5 micron CMOS for high performance at 3.3V. In Proc: Int.Electron Devices Meeting (1988), pp. 52-55.

61

CHEN, H. C., LI, S. S., AND TENG, K. W. Study of bandgap narrowing in the space-charge region of heavily doped silicon MOS capacitors. Solid-State Electronics 32, 5 (1989), 339-344.

62

CHEN, H.-S., AND LI, S. S. Determination of Interface State Density in Small-Geometry MOSFET's by High-Low-Frequency Transconductance. IEEE Electron Device Lett. 12, 1 (1991), 13-15.

63

CHEN, H.-S., AND LI, S. S. A Model for Analyzing the Interface Properties of a Semiconductor-Insulator-Semiconductor Structure - I: Capacitance and Conductance Technique. IEEE Trans.Electron Devices 39, 7 (1992), 1740-1746.

64

CHEN, H.-S., AND LI, S. S. A Model for Analyzing the Interface Properties of a Semiconductor-Insulator-Semiconductor Structure - II: Transient Capacitance Technique. IEEE Trans.Electron Devices 39, 7 (1992), 1747-1751.

65

CHEN, I.-C., COLEMAN, D. J., AND TENG, C. W. Gate Current Injection Initiated by Electron Band-to-Band in MOS Devices. IEEE Electron Device Lett. 10, 7 (1989), 297-300.

66

CHEN, I. C., KAYA, C., AND PATERSON, J. Band-to-Band Tunneling Induced Substrate Hot-Electron (BBISHE) Injection: A New Programming Mechanism for Nonvolatile memory Devices. In Proc: Int.Electron Devices Meeting (1989), pp. 263-266.

67

CHEN, I.-C., TENG, C. W., COLEMAN, D. J., AND NISHIMURA, A. Interface-Trap Enhanced Gate-Induced Leakage Current in MOSFET. IEEE Electron Device Lett. 10, 5 (1989), 216-218.

68

CHEN, I.-C., AND TENG, C. W. A Quantitative Physical Model for the Band-to-Band Tunneling-Induced Substrate Hot Electron Injection in MOS Devices. IEEE Trans.Electron Devices 39, 7 (1992), 1646-1651.

69

CHEN, J., CHAN, T. Y., CHEN, I. C., KO, P. K., AND HU, C. Subbreakdown Drain Leakage Current in MOSFET. IEEE Electron Device Lett. EDL-8, 11 (1987), 515-517.

70

CHEN, J., CHAN, T., KO, P. K., AND HU, C. Gate Current in OFF-State MOSFET. IEEE Electron Device Lett. 10, 5 (1989), 203-205.

71

CHEN, J.-W., KO, R. J., BRZEZINSKI, D. W., FORBES, L., AND DELL'OCA, C. J. Bulk Traps in Silicon-on-Sapphire by Conductance DLTS. IEEE Trans.Electron Devices ED-28, 3 (1981), 299-304.

72

CHEN, M.-L., LEUNG, C.-W., COCHRAN, W. T., JÜNGLING, W., DZIUBA, C., AND YANG, T. Suppression of Hot-Carrier Effects in Submicrometer CMOS Technology. IEEE Trans.Electron Devices 35, 12 (1988), 2210-2220.

73

CHEN, M.-J. Effect of Back-Gate Bias on Tunneling Leakage in a Gated p-n Diode. IEEE Electron Device Lett. 12, 5 (1991), 249-251.

74

CHEN, W., AND MA, T.-P. Channel-hot-carrier induced oxide charge trapping in NMOSFET's. In Proc: Int.Electron Devices Meeting (1991), pp. 731-734.

75

CHEN, W., AND MA, T.-P. A New Technique for Measuring Lateral Distribution of Oxide Charge and Interface Traps Near MOSFET Junctions. IEEE Electron Device Lett. 12, 7 (1991), 393-395.

76

CHEN, W., BALASINSKI, A., ZHANG, B., AND MA, T.-P. Hot-Carrier Effects on Interface-Trap Capture Cross Sections in MOSFET's as Studied by Charge Pumping. IEEE Electron Device Lett. 13, 4 (1992), 201-202.

77

CHEN, W., AND MA, T.-P. Oxide Charge Buildup and Spread-out During Channel-Hot-Carrier Injection in NMOSFET's. IEEE Electron Device Lett. 13, 6 (1992), 319-321.

78

CHEN, W., BALASINSKI, A., AND MA, T.-P. Lateral Profiling of Oxide Charge and Interface Traps Near MOSFET Junctions. IEEE Trans.Electron Devices 40, 1 (1993), 187-196.

79

CHEN, Y.-Z., AND TANG, T.-W. Numerical Simulation of Avalanche Hot-Carrier Injection in Short-Channel MOSFET's. IEEE Trans.Electron Devices 35, 12 (1988), 2180-2188.

80

CHENG, Y. C., AND SULLIVAN, E. A. Relative importance of phonon scattering to carrier mobility in Si surface layer at room temperature. J.Appl.Phys. 44, 8 (1973), 3619-3625.

81

CHU, C. L., SARASWAT, K. C., AND WONG, S. S. Characterization of lateral dopant diffusion in silicides. In Proc: Int.Electron Devices Meeting (1990), pp. 245-248.

82

CHU, C. L., CHIN, G., SARASWAT, K. C., WONG, S. S., AND DUTTON, R. Technology Limitations for N/P Polycide Gate CMOS due to Lateral Dopant Diffusion in Silicide/Polysilicon Layers. IEEE Electron Device Lett. 12, 12 (1991), 696-698.

83

CHUNG, J. E., AND MULLER, R. S. The development and application of a Si-SiO interface-trap measurement system based on the staircase charge-pumping technique. Solid-State Electronics 32, 10 (1989), 867-882.

84

COBBOLD, R. S. C. Theory and Applications of Field-Effect Transistors. Wiley-Interscience, New York (N.Y.), 1970.

85

CODY, W. J., AND HENRY C. THACHER, J. Rational Chebyshev Approximations for Fermi-Dirac Integrals of Orders , and . Math.Comp. (1967), 30-40.

86

COHEN, M. L., AND BERGSTRESSER, T. K. Band Structures and Pseudopotential Form Factors for Fourteen Semiconductors of the Diamond and Zinc-blende Structures. Physical Review 141, 2 (1966), 789-796.

87

COLLINS, T. W., AND CHURCHILL, J. N. Exact Modeling of the Transient Response of an MOS Capacitor. IEEE Trans.Electron Devices ED-22, 3 (1975), 90-101.

88

CONG, H. V. Tunnel diode reverse characteristics at different temperatures. Solid-State Electronics 24 (1981), 495-500.

89

CONG, H. V. New series representation of Fermi-Dirac integral for arbitraty , and its effect on for integer . Solid-State Electronics 34, 5 (1991), 489-492.

90

CONG, H. V., AND DOAN-KHANH, B. Simple accurate general expression of the Fermi-Dirac integral for arbitrary and . Solid-State Electronics 35, 7 (1992), 949-951.

91

CONLEY, J. W., AND MAHAN, G. D. Tunneling Spectroscopy in GaAs. Physical Review 161, 3 (1967), 681-695.

92

COTTRELL, P. E., TROUTMAN, R. R., AND NING, T. H. Hot-Electron Emission in N-Channel IGFET's. IEEE Trans.Electron Devices ED-26, 4 (1979), 520-533.

93

DAVARI, B., CHANG, W. H., WORDEMAN, M. R., OH, C. S., TAUR, Y., PETRILLO, K. E., MOY, D., BUCCIGNANO, J. J., NG, H. Y., ROSENFIELD, M. G., HOHN, F. J., AND RODRIGUEZ, M. D. A high performance 0.25 CMOS technology. In Proc: Int.Electron Devices Meeting (1988), pp. 56-59.

94

DE GRAAFF, H. C., SLOTBOOM, J. W., AND SCHMITZ, A. The emitter efficiency of bipolar transistors. Solid-State Electronics 20 (1977), 515-521.

95

DE WIELE, F. V. On the flat-band voltage of MOS structures on nonuniformly doped substrates. Solid-State Electronics 27, 8/9 (1984), 824-826.

96

DEN BOSCH, G. V., GROESENEKEN, G., HEREMANS, P., AND MAES, H. E. A new pumping procedure to measure interface trap energy distribution on MOSFETs. In Proc: ESSDERC (Nottingham (U.K.), 1990), Adam Hilger, pp. 579-582.

97

DEN BOSCH, G. V., GROESENEKEN, G. V., HEREMANS, P., AND MAES, H. E. Spectroscopic Charge Pumping: A New Procedure for Measuring Interface Trap Distribution on MOS Transistors. IEEE Trans.Electron Devices 38, 8 (1991), 1820-1831.

98

DEN BOSCH, G. V., GROESENEKEN, G., AND MAES, H. E. On the Geometric Component of Charge-Pumping Current in MOSFET's. IEEE Electron Device Lett. 14, 3 (1993), 107-109.

99

DHARIWAL, S. R., KOTHARI, L. S., AND JAIN, S. C. On the recombination of electrons and holes at traps with finite relaxation time. Solid-State Electronics 24, 8 (1981), 749-752.

100

DIMARIA, D. J., THEIS, T. N., KIRTLEY, J. R., PESAVENTO, F. L., AND DONG, D. W. Electron heating in silicon dioxide and off-stoichiometric silicon dioxide films. J.Appl.Phys. 57, 4 (1985), 1214-1238.

101

DIMARIA, D. J., AND STASIAK, J. W. Trap creation in silicon dioxide produced by hot electrons. J.Appl.Phys. 65, 6 (1989), 2342-2356.

102

DIMARIA, D. J. Temperature dependence of trap creation in silicon dioxide. J.Appl.Phys. 68, 10 (1990), 5234-5246.

103

DOYLE, B. S., AND MISTRY, K. R. Hot-Carrier Stress Damage in the Gate ``Off'' State in n-Channel Transistors. IEEE Trans.Electron Devices 39, 7 (1992), 1774-1776.

104

DOYLE, B., BOURCERIE, M., MARCHETAUX, J.-C., AND BOUDOU, A. Interface State Creation and Charge Trapping in the Medium-to-High Gate Voltage Range () During Hot-Carrier Stressing of n-MOS Transistors. IEEE Trans.Electron Devices 37, 3 (1990), 744-754.

105

DOYLE, B. S., BOURCERIE, M., BERGONZONI, C., BENECCHI, R., BRAVIS, A., MISTRY, K. R., AND BOUDOU, A. The Generation and Characterization of Electron and Hole Traps Created by Hole Injection During Low Gate Voltage Hot-Carrier Stressing of n-MOS Transistors. IEEE Trans.Electron Devices 37, 8 (1990), 1869-1876.

106

DOYLE, B. S., AND MISTRY, K. R. A Lifetime Prediction Method for Hot-Carrier Degradation in Surface-Channel p-MOS Devices. IEEE Trans.Electron Devices 37, 5 (1990), 1301-1307.

107

DOYLE, B. S., MISTRY, K. R., BOURCERIE, M., BERGONZONI, C., BENECCHI, R., BRAVIS, A., AND BOUDOU, A. Reply on comment on ``The Generation and Characterization of Electron and Hole Traps Created by Hole Injection During Low Gate Voltage Hot-Carrier Stressing of n-MOS Transistors''. IEEE Trans.Electron Devices 39, 2 (1992), 460-464.

108

DOYLE, B. S., AND MISTRY, K. R. The Characterization of Hot-Carrier Damage in p-Channel Transistors. IEEE Trans.Electron Devices 40, 1 (1993), 152-156.

109

DUKE, C. B. Tunneling in Solids. In: Solid State Physics: Advances in Research and Applications, F. Seitz, D. Turnbull, and H. Ehrenreich, Eds. Academic Press Inc., New York and London, 1969.

110

DUMKE, W. P. Comparison of band-gap shrinkage observed in luminescence from -Si with that from transport and optical absorption measurements. Appl.Phys.Lett. 42, 2 (1983), 196-198.

111

DUVVURY, C., REDWINE, D. J., AND STIEGLER, H. J. Leakage Current Degradation in N-MOSFET's Due to Hot-Electron Stress. IEEE Electron Device Lett. 9, 11 (1988), 579-581.

112

EADES, W. D., AND SWANSON, R. M. Improvements in the determination of interface state density using deep level transient spectroscopy. J.Appl.Phys. 56, 6 (1984), 1744-1751.

113

EBEL, M. S., GIONIS, J., AND REGITZ, W. M. A 4096-Bit High-Speed Emitter-Coupled-Logic (ECL) Compatible Random-Access Memory. IEEE J.Solid-State Circuits SC-10, 5 (1975), 262-267.

114

EITAN, B., AND FROHMAN-BENTCHKOWSKY, D. Hot-Electron Injection into the Oxide in n-Channel MOS Devices. IEEE Trans.Electron Devices ED-28, 3 (1981), 328-340.

115

EL-SAYED, M., AND HADDARA, H. Study of interface trap properties in MOSFETs using split-current measurements. Solid-State Electronics 34, 2 (1991), 173-180.

116

ELEWA, T., KLEVELAND, B., CRISTOLOVEANU, S., BOUKRISS, B., AND CHOVET, A. Detailed Analysis of Edge Effects in SIMOX-MOS Transistors. IEEE Trans.Electron Devices 39, 4 (1992), 874-882.

117

ELLIOT, A. B. M. The use of charge pumping currents to measure surface state densities in MOS transistors. Solid-State Electronics 19 (1976), 241-247.

118

ENDOH, T., SHIROTA, R., MOMODOMI, M., AND MASUOKA, F. An Accurate Model of Subbreakdown Due to Band-to-Band Tunneling and Some Applications. IEEE Trans.Electron Devices 37, 1 (1990), 290-296.

119

FAGGIN, F., AND KLEIN, T. Silicon Gate Technology. Solid-State Electronics 13 (1970), 1125-1144.

120

FANG, P., HUNG, K. K., KO, P. K., AND HU, C. Characterizing a Single Hot-Electron-Induced Trap in Submicron MOSFET Using Random Telegraph Noise. In Proc: VLSI Technology Symp. (Honolulu (Hawaii), 1990), pp. 37-38.

121

FANG, P., HUNG, K. K., KO, P. K., AND HU, C. Hot-Electron-Induced Traps Studied Through the Random Telegraph Noise. IEEE Electron Device Lett. 12, 6 (1991), 273-275.

122

FAZAN, P. C., MATHEWS, V. K., SANDLER, N., LO, G. Q., AND KWONG, D. L. A High-C Capacitor () with Ultrathin CVD-TaO Films Deposited on Rugged Poly-Si for High Density DRAMs. In Proc: Int.Electron Devices Meeting (1992), pp. 263-266.

123

FENG, W.-S., CHAN, T. Y., AND HU, C. MOSFET Drain Breakdown Voltage. IEEE Electron Device Lett. EDL-7, 7 (1986), 449-450.

124

FISCHETTI, M. V., GASTALDI, R., MAGGIONI, F., AND MODELLI, A. Slow and fast states induced by hot electrons at Si-SiO interface. J.Appl.Phys. 53, 4 (1982), 3136-3144.

125

FISCHETTI, M. V., DIMARIA, D. J., BRORSON, S. D., THEIS, T. N., AND KIRTLEY, J. R. Theory of high-field electron transport in silicon dioxide. Physical Review B 31, 12 (1985), 8124-8142.

126

FISCHETTI, M. V., AND DIMARIA, D. J. Hot electrons in SiO: Ballistic to steady-state transport. Solid-State Electronics 31, 3/4 (1988), 629-636.

127

FISCHETTI, M. V., LAUX, S. E., AND DIMARIA, D. J. The physics of hot-electron degradation of Si MOSFET's: Can we understand it? Appl.Surf.Science 39 (1989), 578-596.

128

FISCHETTI, M. V. Generation of positive charge in silicon dioxide during avalanche and tunnel electron injection. J.Appl.Phys. 57, 8 (1985), 2860-2879.

129

FISCHETTI, M. V. Model for the generation of positive charge at the Si-SiO interface based on hot-hole injection from the anode. Physical Review B 31, 4 (1985), 2099-2113.

130

FISCHETTI, M. V., AND LAUX, S. E. Monte Carlo analysis of electron transport in small semiconductor devices including band-structure and space-charge effects. Physical Review B 38, 14 (1988), 9721-9745.

131

FISHBEIN, B., KRAKAUER, D., AND DOYLE, B. Measurement of Very Low Tunneling Current Density in SiO Using the Floating-Gate Technique. IEEE Electron Device Lett. 12, 12 (1991), 713-715.

132

FISHBEIN, B. J., AND JACKSON, D. B. Performance Degradation of N-Channel MOS Transistors During DC and Pulsed Fowler-Nordheim Stress. In Proc: Int. Reliability Physics Symp. (1990), pp. 159-163.

133

FITZGERALD, D. J., AND GROVE, A. S. Surface recombination in semiconductors. Surface Science 9 (1968), 347-369.

134

FLEISCHER, S., LIU, Z. H., LAI, P. T., MA, Z. J., AND CHENG, Y. C. The Effects of Nitridation and Re-Oxidation on Drain Leakage Current in n-Channel MOSFETs. In Proc: Int.Conf. on Solid-State Devices and Materials (Sendai (Japan), 1990), pp. 1153-1154.

135

FOWLER, R. H. The analysis of photoelectric sensitivity curves for clean metals at various temperatures. Physical Review 38 (1931), 45-55.

136

FRANTSUZOV, A. A., OKHONIN, S. A., AND POGOSOV, A. G. The Influence of Quantization on the Space-Charge Layer Capacitance of Si in Strong Accumulation. physica status solidi (b) 136 (1986), 241-249.

137

FU, H.-S., AND SAH, C.-T. Theory and Experiments on Surface Noise. IEEE Trans.Electron Devices ED-19, 2 (1972), 273-285.

138

FUJII, E., UEMOTO, Y., HAYASHI, S., NASU, T., SHIMADA, Y., MATSUDA, A., KIBE, M., AZUMA, M., OTSUKI, T., KANO, G., SCOTT, M., MCMILLAN, L. D., AND DE ARAUJO, C. A. P. ULSI DRAM Technology with BaSrTiO Film of 1.3nm Equivalent SiO Thickness and Leakage Current. In Proc: Int.Electron Devices Meeting (1992), pp. 267-270.

139

GAENSSLEN, F. H., AND JAEGER, R. C. Temperature dependent threshold behavior of depletion mode MOSFETs. Solid-State Electronics 22 (1979), 423-430.

140

GAENSSLEN, F. H., AND AITKEN, J. M. Sensitive Technique for Measuring Small MOS Gate Currents. IEEE Electron Device Lett. EDL-1, 11 (1980), 231-233.

141

GAENSSLEN, F. H., AND JAEGER, R. C. Low Temperature Microelectronics. In Proc: Int.Conf. on Solid-State Devices and Materials (Sendai (Japan), 1990), pp. 353-356.

142

GAUTIER, J., GUEGAN, G., GUERIN, M., AND LERME, M. Operation of Short-Channel Depletion-Mode MOS Devices at Liquid-Nitrogen Temperature. IEEE Trans.Electron Devices 38 (1991), 1832-1839.

143

GEISSLER, S., PORTH, B., LASKY, J., JOHNSON, J., AND VOLDMAN, S. A New Three-Dimensional MOSFET Gate-Induced Drain Leakage Effect in Narrow Deep Submicron Devices. In Proc: Int.Electron Devices Meeting (1991), pp. 839-842.

144

GHIBAUDO, G., AND SAKS, N. S. A time domain analysis of the charge pumping current. J.Appl.Phys. 64, 9 (1988), 4751-4754.

145

GHIBAUDO, G., AND SAKS, N. S. Investigation of the charge pumping current in metal-oxide-semiconductor structures. J.Appl.Phys. 65, 11 (1989), 4311-4318.

146

GHODSI, R., YEOW, Y. T., LING, C. H., AND ALAM, M. K. Evaluation of Localised Trapped Charge and Interface States in MOSFET's Through Gate Capacitances Measurement. In Proc: Int.Conf. on Solid-State Devices and Materials (Tsukuba (Japan), 1992), pp. 505-507.

147

GOANO, M. Series expansion of the Fermi-Dirac integral over the entire domain of real and . Solid-State Electronics 36, 2 (1993), 217-221.

148

GOETZBERGER, A., AND NICOLLIAN, E. H. U.S. Patent 3,523,190. filed October 17, 1968; issued August 4, 1970.

149

GOGUENHEIM, D., AND VUILLAUME, D. Accurate measurements of capture cross sections of semiconductor insulator interface states by a trap-filling experiment: The charge-potential feedback effect. J.Appl.Phys. 68, 3 (1990), 1104-1113.

150

GOLDER, J., AND BALDINGER, E. Untersuchung des Zusammenhangs zwischen Grenzschichtzuständen und Charge Pumping-Effekt bei MOS-Transistoren. Hevl.Phys.Acta 44 (1971), 387-400.

151

GOLDSMAN, N., AND FREY, J. Electron energy distribution for calculation of gate leakage current in MOSFETs. Solid-State Electronics 31, 6 (1988), 1089-1092.

152

GRADSHTEYN, I. S., AND RYZHIK, I. M. Table of Integrals, Series and Products. Academic Press Inc., Harcourt Brace Jovanovic, 1980.

153

GREVE, D. W., POTYRAJ, P. A., AND GUZMAN, A. M. Field-enhanced emission and capture in polysilicon junctions. Solid-State Electronics 28, 12 (1985), 1255-1261.

154

GROESENEKEN, G., MAES, H. E., BELTRA'N, N., AND KEERSMAECKER, R. F. D. A Reliable Approach to Charge-Pumping Measurements in MOS Transistors. IEEE Trans.Electron Devices ED-31, 1 (1984), 42-53.

155

GROSS, B. J., AND SODINI, C. G. 1/f Noise in MOSFET with Ultrathin Gate Dielectrics. In Proc: Int.Electron Devices Meeting (1992), pp. 881-884.

156

GROVE, A. S., AND FITZGERALD, D. J. Surface effects on p-n junctions: Characteristics of surface space-charge regions under non-equilibrium conditions. Solid-State Electronics 9 (1966), 783-806.

157

GROVE, A. S. Physics and Technology of Semiconductor Devices. Wiley, New York (N.Y.), 1967.

158

GROVE, A. S., JR., O. L., AND HOOPER, W. W. Effect of Surface Fields on the Breakdown Voltage of Planar Silicon Junctions. IEEE Trans.Electron Devices ED-14, 3 (1967), 157-162.

159

GUMMEL, H. K. A Self-Consistent Iterative Scheme for One-Dimensional Steady State Transistor Calculations. IEEE Trans.Electron Devices ED-11 (1964), 455-465.

160

HABAS, P., HEINREICHSBERGER, O., LINDORFER, P., PICHLER, P., PÖTZL, H., SCHÜTZ, A., SELBERHERR, S., STIFTINGER, M., AND THURNER, M. MINIMOS 5 - User's Guide. Technical University Vienna, 1990.

161

HABAS, P. Effects of Short-Channel MOS Transistors. Diploma thesis, Faculty of Technical Sciences, Novi Sad (YU), 1985.

162

HABAS, P. Modeling of MOSFET's Accounting for High-Field Effects in the Channel. Mr thesis, Faculty of Electrical Engineering Nikola Tesla, Belgrade (YU), 1989.

163

HABAS, P., AND SELBERHERR, S. Numerical Simulation of MOS-Devices with Non-Degenerate Gate. In Proc: ESSDERC (Nottingham (U.K.), 1989), pp. 161-164.

164

HABAS, P. A physics based analytical MOSFET model with accurate field dependent mobility. Solid-State Electronics 33, 7 (1990), 923-933.

165

HABAS, P., AND SELBERHERR, S. On the effect of non-degenerate doping of polysilicon gate in thin oxide MOS-devices - Analytical modeling. Solid-State Electronics 33, 12 (1990), 1539-1544.

166

HABAS, P., AND SELBERHERR, S. Impact of the Non-Degenerate Gate Effect on the Performance of Submicron MOS-Devices. Journal MIDEM 20, 4 (1991), 185-188.

167

HABAS, P., AND FARICELLI, J. Investigation of the Physical Modeling of the Gate-Depletion Effect. IEEE Trans.Electron Devices 39, 6 (1992), 1496-1500.

168

HABAS, P., HEINREICHSBERGER, O., AND SELBERHERR, S. Analysis of the Degradation of n-Channel LDD MOSFET's by Numerical Simulation of the Charge-Pumping Current. In Proc: ICSICT (Beijing (China), 1992), pp. 691-693.

169

HABAS, P., HEINREICHSBERGER, O., AND SELBERHERR, S. Transient Two-Dimensional Numerical Analysis of the Charge-Pumping Experiment. In Proc: ESSDERC (Leuven (Belgium), 1992), pp. 687-690.

170

HABAS, P., LUGBAUER, A., AND SELBERHERR, S. Two-Dimensional Numerical Modeling of Interband Tunneling Accounting for Nonuniform Electric Field. In Proc: NUPAD Conf. (Seattle (WA), 1992), pp. 135-140.

171

HABAS, P., AND SELBERHERR, S. A Closed-Loop Extraction of the Spatial Distribution of Interface Traps Based on Numerical Model of the Charge-Pumping Experiment. In Proc: Int.Conf. on Solid-State Devices and Materials (Tsukuba (Japan), 1992), pp. 170-172.

172

HABAS, P. A Two-Dimensional Modeling of Hot-Carrier Injection into the Oxide by MINIMOS, 1993. (unpublished manuscript)

173

HACKBARTH, E., AND TANG, D. D.-L. Inherent and Stress-Induced Leakage in Heavily Doped Silicon Junctions. IEEE Trans.Electron Devices 35, 12 (1988), 2108-2118.

174

HADDARA, H., AND CRISTOLOVEANU, S. Profiling of stress induced interface states in short channel MOSFETs using a composite charge pumping technique. Solid-State Electronics 29, 8 (1986), 767-772.

175

HADDARA, H., AND CRISTOLOVEANU, S. Two-Dimensional Modeling of Locally Damaged Short-Channel MOSFET's Operating in the Linear Region. IEEE Trans.Electron Devices ED-34, 2 (1987), 378-385.

176

HADDARA, H., ELEWA, T., AND CRISTOLOVEANU, S. Static and Dynamic Transconductance Model for Depletion-Mode Transistors: A New Characterization Method for Silicon-on-Insulator Materials. IEEE Electron Device Lett. 9, 1 (1988), 35-37.

177

HADDARA, H., AND GHIBAUDO, G. Analytical modeling of transfer admittance in small MOSFETs and application to interface state characterisation. Solid-State Electronics 31, 6 (1988), 1077-1082.

178

HADDARA, H. S., AND EL-SAYED, M. Conductance technique in MOSFETs: Study of interface trap properties in the depletion and weak inversion regimes. Solid-State Electronics 31, 8 (1988), 1289-1298.

179

HALL, R. N. Electron-Hole Recombination in Germanium. Physical Review 87 (1952), 387.

180

HALPERIN, B. I., AND LAX, M. Impurity-Band Tails in the High-Density Limit. I. Minimum Counting Method. Physical Review 148, 4 (1966), 722-740.

181

HAN, C. H., AND KIM, K. Leakage Mechanisms in the Heavily Doped Gated Diode Structures. IEEE Electron Device Lett. 12, 2 (1991), 74-76.

182

HÄNSCH, W. Hot carrier analysis of MOSFET beyond the substrate current criterion. In Proc: VLSI Process/Device Workshop, Kawasaki (Japan) (1990), pp. 156-157.

183

HÄNSCH, W., MAZURE, C., LILL, A., AND ORLOWSKI, M. K. Hot Carrier Hardness Analysis of Submicrometer LDD Devices. IEEE Trans.Electron Devices 38, 3 (1991), 512-517.

184

HARTSTEIN, A., NING, T. H., AND FOWLER, A. B. Electron scattering in silicon inversion layers by oxide and surface roughness. Surface Science 58 (1976), 178-181.

185

HARTSTEIN, A., ALBERT, N. F., BRIGHT, A. A., KAPLAN, S. B., ROBINSON, B., AND TORNELLO, J. A. A metal-oxide-semiconductor field-effect transistor with a 20-nm channel length. J.Appl.Phys. 68, 5 (1990), 2493-2495.

186

HARTSTEIN, A. Fabrication and Measurements of Ultra-Short Silicon MOSFETs. In Proc: Int.Conf. on Solid-State Devices and Materials (Tsukuba (Japan), 1992), pp. 481-484.

187

HAYASHI, T., FUKUDA, H., UCHIYAMA, A., AND IWABUCHI, T. A New Prediction Method for Hot Carrier Degradation of Submicron PMOSFET with Charge Pumping Technique. In Proc: Int.Conf. on Solid-State Devices and Materials (Tsukuba (Japan), 1992), pp. 509-511.

188

HAYASHIDA, H., TOYOSHIMA, Y., SUIZU, Y., MITSUHASHI, K., IWAI, H., AND MAEGUCHI, K. Dopant Redistribution in Dual Gate W-Polycide CMOS and Its Improvement by RTA. In Proc: VLSI Technology Symp. (Kyoto (Japan), 1989), pp. 29-30.

189

HAZAMA, H. Anomalous Band-to-Band Tunneling Current in n-channel MOSFETs. In Proc: Int.Conf. on Solid-State Devices and Materials (Sendai (Japan), 1990), pp. 303-306.

190

HEASELL, E. L. The Emitter Efficiency of Silicon Bipolar Transistors - An Unperturbed Band Model. IEEE Trans.Electron Devices ED-26, 6 (1979), 919-923.

191

HEINREICHSBERGER, O. Transiente Simulation von Silizium-MOSFETs. Dissertation, Technical University Vienna, Vienna (Austria), 1992.

192

HEINREICHSBERGER, O., HABAS, P., AND SELBERHERR, S. Analysis of Geometric-Charge-Pumping Components in a Thin-Film SOI Device. In Proc: ESSDERC (Leuven (Belgium), 1992), pp. 819-822.

193

HENDRIKS, E. A., AND ZIJLSTRA, R. J. J. 1/f Noise in (100) -channel Si-MOSFETs from to . Solid-State Electronics 31, 6 (1988), 1105-1111.

194

HEREMANS, P., BELLENS, R., GROESENEKEN, G., AND MAES, H. E. Consistent Model for the Hot-Carrier Degradation in n-Channel and p-Channel MOSFET's. IEEE Trans.Electron Devices ED-35, 12 (1988), 2194-2209.

195

HEREMANS, P., DEN BOSCH, G. V., BELLENS, R., GROESENEKEN, G., AND MAES, H. E. Understanding of the temperature dependence of channel hot-carrier degradation in the range 77K to 300K. In Proc: Int.Electron Devices Meeting (1989), pp. 67-70.

196

HEREMANS, P., WITTERS, J., GROESENEKEN, G., AND MAES, H. E. Analysis of the Charge Pumping Technique and Its Application for the Evaluation of MOSFET Degradation. IEEE Trans.Electron Devices 36, 7 (1989), 1318-1335.

197

HEREMANS, P., BELLENS, R., GROESENEKEN, G., AND MAES, H. E. Comment on ``The Generation and Characterization of Electron and Hole Traps Created by Hole Injection During Low Gate Voltage Hot-Carrier Stressing of n-MOS Transistors''. IEEE Trans.Electron Devices 39, 2 (1992), 458-460.

198

HEREMANS, P., GROESENEKEN, G., AND MAES, H. E. Hole Trapping During Low Gate Bias, High Drain Bias Hot-Carrier Injection in n-MOSFET's at 77K. IEEE Trans.Electron Devices 39, 4 (1992), 851-857.

199

HEYNS, M. M., RAO, D. K., AND KEERSMAECKER, R. F. D. Oxide field dependence of Si-SiO interface state generation and charge trapping during electron injection. Appl.Surf.Science 39 (1989), 327-338.

200

HICKMOTT, T. W., AND ISAAC, R. D. Barrier heights at the polycrystalline silicon-SiO interface. J.Appl.Phys. 52, 5 (1981), 3464-3475.

201

HIGMAN, J. M., HESS, K., HWANG, C. G., AND DUTTON, R. W. Coupled Monte Carlo-Drift Diffusion Analysis of Hot-Electron Effects in MOSFET's. IEEE Trans.Electron Devices 36, 5 (1989), 930-937.

202

HILLENIUS, S. J., LIU, R., GEORGIOU, G. E., FIELD, R. L., WILLIAMS, D. S., KORNBLIT, A., BUOLIN, D. M., JOHNSTON, R. L., AND LYNCH, W. T. A Symmetric Submicron CMOS Technology. In Proc: Int.Electron Devices Meeting (1986), pp. 252-255.

203

HO, C. P., PLUMMER, J. D., HANSEN, S. E., AND DUTTON, R. W. VLSI Process Modeling - SUPREM III. IEEE Trans.Electron Devices 30, 11 (1983), 1438-1453.

204

HOEFFLINGER, B. Output Characteristics of Short-Channel Field-Effect Transistors. IEEE Trans.Electron Devices ED-28, 8 (1981), 971-976.

205

HOFMANN, F., AND HÄNSCH, W. The charge pumping method: Experiment and complete simulation. J.Appl.Phys. 66, 7 (1989), 3092-3096.

206

HOFMANN, F., AND KRAUTSCHNEIDER, W. K. A simple technique for determining the interface-trap distribution of submicron metal-oxide-semiconductor transistors by the charge pumping method. J.Appl.Phys. 65, 3 (1989), 1358-1360.

207

HOFMANN, F. Interface states extracted from gated diode and charge pumping measurements. In Proc: ESSDERC (Nottingham (U.K.), 1990), Adam Hilger, pp. 583-586.

208

HOFMANN, K. R., WERNER, C., WEBER, W., AND DORDA, G. Hot-Electron and Hole-Emission Effects in Short n-Channel MOSFET's. IEEE Trans.Electron Devices ED-32, 3 (1985), 691-699.

209

HOFSTEIN, S. R., AND HEIMAN, F. P. The Silicon Insulated-Gate Field-Effect Transistor. Proc.IEEE 51 (1963), 1190-1202.

210

HOFSTEIN, S. R., AND WARFIELD, G. Carrier Mobility and Current Saturation in the MOS Transistor. IEEE Trans.Electron Devices, 3 (1965), 129-138.

211

HOFSTEIN, S. R., AND WARFIELD, G. The Insulated Gate Tunnel Junction Triode. IEEE Trans.Electron Devices ED-12, 2 (1965), 66-76.

212

HOMILIUS, V. J., AND FRANZ, W. Theorie der inneren Feldemission in kubischen Kristallen. Z.Naturforschung 9a (1954), 205-210.

213

HORI, T. Drain-Structure Design for Reduced Band-to-Band and Band-to-Defect Tunneling Leakage. In Proc: VLSI Technology Symp. (Honolulu (Hawaii), 1990), pp. 69-70.

214

HOUDT, J. V., HEREMANS, P., WITTERS, J. S., GROESENEKEN, G., AND MAES, H. E. Study of the enhanced hot-electron injection in split-gate transistor structures. In Proc: ESSDERC (Nottingham (U.K.), 1990), Adam Hilger, pp. 261-264.

215

HSU, F.-C., AND TAM, S. Relationship Between MOSFET Degradation and Hot-Electron-Induced Interface-State Generation. IEEE Electron Device Lett. EDL-5, 2 (1984), 50-52.

216

HU, C. Lucky-Electron Model of Channel Hot Electron Emission. In Proc: Int.Electron Devices Meeting (1979), pp. 22-25.

217

HU, C., TAM, S. C., HSU, F.-C., KO, P.-K., CHAN, T.-Y., AND TERRILL, K. W. Hot-Electron-Induced MOSFET Degradation-Model, Monitor, and Improvement. IEEE Trans.Electron Devices ED-32, 2 (1985), 375-385.

218

HUNG, K. K., AND CHENG, Y. C. Determination of Si-SiO interface trap properties of p-MOS structures with very thin oxides by conductance measurement. Appl.Surf.Science 30 (1987), 114-119.

219

HUNG, K. K., KO, P. K., HU, C., AND CHENG, Y. C. An Automated System for Measurement of Random Telegraph Noise in Metal-Oxide-Semiconductor Field-Effect Transistors. IEEE Trans.Electron Devices 36, 6 (1989), 1217-1219.

220

HUNG, K. K., KO, P. K., HU, C., AND CHENG, Y. C. Random Telegraph Noise of Deep-Submicrometer MOSFET's. IEEE Electron Device Lett. 11, 2 (1990), 90-92.

221

HURKX, G. A. M., PEEK, H. L., SLOTBOOM, J. W., AND WINDGASSEN, R. A. Anomalous Behaviour of Surface Leakage Currents in Heavily-Doped MOS Structure. In Proc: Int.Electron Devices Meeting (1992), pp. 919-922.

222

HWANG, W., POON, E., AND CARD, H. C. Carrier recombination at grain boundaries and the effective recombination velocity. Solid-State Electronics 26, 6 (1983), 599-603.

223

IGURA, Y., MATSUOKA, H., AND TAKEDA, E. New Device Degradation Due to ``Cold'' Carriers Created by Band-to-Band Tunneling. IEEE Electron Device Lett. 10, 5 (1989), 227-229.

224

IHANTOLA, H. K. J., AND MOLL, J. L. Design Theory of a Surface Field-Effect Transistor. Solid-State Electronics 7 (1964), 423-430.

225

IWAI, H. Hot carrier-induced degradation modes in thin-gate insulator dual-gate MISFETs. In Proc: Int.Conf. on Insulating Films on Semicond. (INFOS) (Liverpool (U.K.), 1991), pp. 83-92.

226

IWASE, M., AND ICHI TAKAGI, S. Effects of Depleted Poly-Si Gate on MOSFET Performance. In Proc: Int.Conf. on Solid-State Devices and Materials (Sendai (Japan), 1990), pp. 271-274.

227

IWATA, S., YAMAMOTO, N., KOBAYASHI, N., TERADA, T., AND MIZUTANI, T. A New Tungsten Gate Process for VLSI Applications. IEEE Trans.Electron Devices ED-31, 9 (1984), 1174-1179.

228

JÄNTSCH, O., AND BORCHERT, B. Determination of interface state density especially at the band edges by noise measurements on MOSFETs. Solid-State Electronics 30, 10 (1987), 1013-1015.

229

JEN WANN, H., KO, P. K., AND HU, C. Gate-Induced Band-to-band Tunneling Leakage Current in LDD MOSFETs. In Proc: Int.Electron Devices Meeting (1992), pp. 150-147.

230

JIMENEZ-TEJADA, J. A., LOPEZ-VILLANUEVA, J. A., CARTUJO, P., VICENTE, J., AND CARCELLER, J. E. Importance of the Choice of the Profile Model for a Junction in the Location of Deep Levels. J.Electronic Materials 21, 9 (1992), 883-886.

231

JOHNSON, J. B., VOLDMAN, S. H., AND LINTON, T. D. Discretization methods and physical models for simulating leakage currents in semiconductor devices with application to modeling trench-DRAM cells. COMPEL 10, 4 (1991), 573-588. (selected full-length papers from NASECODE VII Conf.)

232

KADEN, G., AND REIMER, H. MOS-Strukturen mit sperrseitig vorgespanntem externem pn-Übergang bei linearer Gatespannungsansteuerung, I. Impulsstromverhalten. physica status solidi (a) 53 (1979), 195-206.

233

KADEN, G., AND REIMER, H. MOS-Strukturen mit sperrseitig vorgespanntem externem pn-Übergang bei linearer Gatespannungsansteuerung, II. Bestimmung von und . physica status solidi (a) 59 (1980), 719-729.

234

KAHNG, D., AND ATALLA, M. M. Silicon-Silicon Dioxide Field Induced Devices. In Proc: Device Research Conf., Pittsburgh (Pa) (1960).

235

KAMINS, T. I. Hall Mobility in Chemically Deposited Polycrystalline Silicon. J.Appl.Phys. 42, 11 (1971), 4357-4365.

236

KANE, E. O. Zener tunneling in semiconductors. Journal Phys.Chem.Solids 12 (1959), 181-188.

237

KANE, E. O. Theory of Tunneling. J.Appl.Phys. 32, 1 (1961), 83-91.

238

KANE, E. O. Thomas-Fermi Approach to Impure Semiconductor Band Structure. Physical Review 131, 1 (1963), 79-88.

239

KANE, E. O. Band tails in semiconductors. Solid-State Electronics 28, 1/2 (1985), 3-10.

240

KAPLAN, G. Determination of interface state density and capture cross section by a hysteresis pulsed C-V method. Solid-State Electronics 24 (1981), 87-89.

241

KARMANN, A., AND SCHULZ, M. Individual attractive defect centers in the Si-SiO interface. In Proc: Int.Conf. on Insulating Films on Semicond. (INFOS) (Liverpool (U.K), 1991), pp. 143-146.

242

KATSUBE, T., SAKATA, I., AND IKOMA, T. Hot Hole Effect on Surface-State Density and Minority-Carrier Generation Rates in Si-MOS Diodes Measured by DLTS. IEEE Trans.Electron Devices ED-27, 7 (1980), 1238-1243.

243

KEJHAR, M. Double-Pulse Charge Pumping in MOSFET's. IEEE Electron Device Lett. 13, 6 (1992), 344-346.

244

KELDYSH, L. V. Behavior of non-metallic crystals in strong electric field. Soviet Physics-Solid State 6(33), 4 (1958), 763-770.

245

KELDYSH, L. V. Influence of the lattice vibrations of a crystal on the production of electron-hole pairs in a strong electrical field. Soviet Physics-Solid State 34(7), 4 (1958), 665-669.

246

KIM, C.-K., AND LENZLINGER, M. Charge Transfer in Charge-Coupled Devices. J.Appl.Phys. 42, 9 (1971), 3586-3594.

247

KIM, D. M., KHONDKER, A. N., SHAH, R. R., AND JR., D. L. C. Conduction in Polycrystalline Silicon: Diffusion Theory and Extended State Mobility Model. IEEE Electron Device Lett. EDL-3, 5 (1982), 141-143.

248

KIM, K. T., KANG, L. G., PARK, T. S., SHIN, Y. S., PARK, J. K., LEE, C. J., HWANG, C. G., CHIN, D., AND PARK, Y. E. Tungsten silicide/titanium nitride compound gate for submicron CMOSFET. In Proc: VLSI Technology Symp. (Honolulu (Hawaii), 1990), pp. 115-116.

249

KING, T.-J., PFIESTER, J. R., SHOTT, J. D., MCVITTIE, J. P., AND SARASWAT, K. C. A Polycrystalline-SiGe-Gate CMOS Technology. In Proc: Int.Electron Devices Meeting (1990), pp. 253-256.

250

KING, T.-J., PFIESTER, J. R., AND SARASWAT, K. C. A Variable-Work-Function Polycrystalline-SiGe Gate Material for Submicrometer CMOS Technologies. IEEE Electron Device Lett. 12, 10 (1991), 533-535.

251

KIRTON, M. J., AND UREN, M. J. Capture and emission kinetics of individual Si:SiO interface states. Appl.Phys.Lett. 48, 19 (1986), 1270-1272.

252

KLAASSEN, D. B. M., SLOTBOOM, J. W., AND DE GRAAFF, H. C. Unified apparent bandgap narrowing in - and -type silicon. Solid-State Electronics 35, 2 (1992), 125-129.

253

KLAASSEN, F. M. Characterization of Low 1/f Noise in MOS Transistors. IEEE Trans.Electron Devices ED-18 (1971), 887-891.

254

KOBAYASHI, N., IWATA, S., YAMAMOTO, N., MIZUTANI, T., AND YAGI, K. Tungsten gate technology using wet hydrogen oxidation. In Proc: Int.Electron Devices Meeting (1984), pp. 122-125.

255

KOCH, F., BOLLU, M., AND ASENOV, A. MOSFETs Under Electrical Stress - Degradation, Subthreshold Conduction, and Noise in a Submicron Structure. In: Physics and Technology of Submicron Structures, H. Heinrich, G. Bauer, and F. Kuchar, Eds., vol. 83. Springer-Verlag, 1988, pp. 253-262. Springer Series in Solid-State Sciences.

256

KOOMEN, J. Investigation of the MOST channel conductance in weak inversion. Solid-State Electronics 16 (1973), 801-810.

257

KOYANAGI, M., WU, I.-W., LEWIS, A. G., FUSE, M., AND BRUCE, R. Evaluation of polycrystalline silicon thin film transistors with the charge pumping technique. In Proc: Int.Electron Devices Meeting (1990), pp. 863-866.

258

KOYANAGI, M., BABA, Y., HATA, K., WU, I.-W., LEWIS, A. G., FUSE, M., AND BRUCE, R. The Charge-Pumping Technique for Grain Boundary Trap Evaluation in Polysilicon TFT's. IEEE Electron Device Lett. 13, 3 (1992), 152-154.

259

KUO, J. B., DUTTON, R. W., AND WOOLEY, B. A. MOS Pass Transistor Turn-Off Transient Analysis. IEEE Trans.Electron Devices ED-33, 10 (1986), 1545-1555.

260

KURIMOTO, K., ODAKE, Y., AND ODANAKA, S. Drain leakage current characteristics due to the band-to-band tunneling. In Proc: Int.Electron Devices Meeting (1989), pp. 621-624.

261

KURINO, H., HASHIMOTO, H., HIRUMA, Y., FUJIMORI, T., AND KOYANAGI, M. Photon Emission from 70nm Gate Length MOSFET's. In Proc: Int.Electron Devices Meeting (1992), pp. 1015-1018.

262

KWASNICK, R. F., KAMINSKY, E. B., FRANK, P. A., FRANZ, G. A., POLASKO, K. J., SAIA, R. J., AND GORCZYA, T. B. An Investigation of Molybdenum Gate for Submicrometer CMOS. IEEE Trans.Electron Devices 35, 9 (1988), 1432-1438.

263

LAI, S. K. Two-carrier nature of interface-state generation in hole trapping and radiation damage. Appl.Phys.Lett. 39, 1 (1981), 58-60.

264

LANG, D. V. Deep-level transient spectroscopy: A new method to characterize traps in semiconductors. J.Appl.Phys. 45, 7 (1974), 3023-3032.

265

LANZONI, M., SANGIORGI, E., FIEGNA, C., MANFREDI, M., AND RICCÓ, B. Extended (1.1-2.9 eV) hot-carrier induced photon emission in n-channel MOSFETs. In Proc: Int.Electron Devices Meeting (1990), pp. 69-72.

266

LEBURTON, J. P., GESCH, H., AND DORDA, G. Analytical approach of hot electron transport in small size MOSFET's. Solid-State Electronics 24, 8 (1981), 763-771.

267

LEE, D. S., AND FOSSUM, J. G. Energy-Band Distorsion in Highly Doped Silicon. IEEE Trans.Electron Devices ED-30, 6 (1983), 626-634.

268

LEE, G.-Y. Characterization of SOI-MOSFET with a new measurement technique; channel conductance transient spectroscopy (CCTS). In Proc: ICVC (Seoul (Korea), 1991), pp. 260-263.

269

LEE, S.-W., LIANG, C., PAN, C.-S., LIN, W., AND MARK, J. B. A Study on the Physical Mechanism in the Recovery of Gate Capacitance to in Implanted Polysilicon MOS Structures. IEEE Electron Device Lett. 13, 1 (1992), 2-4.

270

LENZLINGER, M., AND SNOW, E. H. Fowler-Nordheim Tunneling into Thermally Grown SiO. J.Appl.Phys. 40, 1 (1969), 278-283.

271

LI, X. M., AND DEEN, M. J. A new charge pumping method for determining the spatial interface state density distribution in MOSFETs. In Proc: Int.Electron Devices Meeting (1990), pp. 85-88.

272

LI, X. M., AND DEEN, M. J. Determination of interface state density in MOSFETs using the spatial profiling charge pumping technique. Solid-State Electronics 35, 8 (1992), 1059-1063.

273

LIBERA, G. D., AND BERGONZONI, C. Physical characterization of stressed n-MOSFETs using a novel approach to the charge pumping technique measurements. In Proc: ICVC (Seoul (Korea), 1991), pp. 183-186.

274

LIFSHITZ, N., AND LURYI, S. Influence of a Resistive Sublayer at the Polysilicon/Silicon Dioxide Interface on MOS Properties. IEEE Trans.Electron Devices ED-30, 7 (1983), 833-836.

275

LIFSHITZ, N. Dependence of the Work-Function Difference Between the Polysilicon Gate and Silicon Substrate on the Doping Level in Polysilicon. IEEE Trans.Electron Devices ED-32, 3 (1985), 617-621.

276

LIN, W., CHEN, M. L., DOKLAN, R. H., AND LU, C. Y. Dopant diffusion in poly gate CMOS process. Solid-State Electronics 32, 11 (1989), 965-969.

277

LING, C. H., YEOW, Y. T., AND AH, L. K. Characterization of Charge Trapping in Submicrometer NMOSFET's by Gate Capacitance Measurements. IEEE Electron Device Lett. 13, 11 (1992), 587-589.

278

LO, G.-Q., AND KWONG, D.-L. Roles of oxide trapped charge and generated interface states on GIDL under hot-carrier stressing. In Proc: Int.Electron Devices Meeting (1990), pp. 557-560.

279

LO, G. Q., JOSHI, A. B., AND KWONG, D.-L. Hot-Carrier-Stress Effects on Gate-Induced Drain Leakage Current in n-Channel MOSFET's. IEEE Electron Device Lett. 12, 1 (1991), 5-7.

280

LOWNEY, J. R. Band-gap narrowing in the space-charge region of heavily doped silicon diodes. Solid-State Electronics 28, 1/2 (1985), 187-191.

281

LU, C.-Y., SUNG, J., KIRSCH, H. C., HILLENIUS, S. J., SMITH, T., AND MANCHANDA, L. Anomalous C-V Characteristics of Implanted Poly MOS Structure in n/p Dual-Gate CMOS Technology. IEEE Electron Device Lett. 10, 5 (1989), 192-194.

282

LYU, J.-S., NAM, K.-S., AND LEE, C. Determination of the Interface Trap Density in MOSFETs from the Subthreshold Slope Measurements. In Proc: Int.Conf. on Solid-State Devices and Materials (Tsukuba (Japan), 1992), pp. 167-169.

283

LYUMKIS, E. D., POLSKY, B. S., SHUR, A. I., AND VISOCKY, P. Transient semiconductor device simulation including energy balance equation. COMPEL II, 2 (1992), 311-325.

284

MA, Z. J., LAI, P. T., CHENG, Y. C., AND HUANG, M. Q. Instability in GIDL current of thermally-nitrided-oxide N-MOSFET's. In Proc: ICVC (Seoul (Korea), 1991), pp. 191-194.

285

MA, Z. J., LAI, P. T., AND CHENG, Y. C. Oxide-Trap-Induced Instability in GIDL of Thermally Nitrided-Oxide N-MOSFET's Under Stress. IEEE Electron Device Lett. 13, 2 (1992), 77-79.

286

MA, Z. J., LAI, P. T., AND CHENG, Y. C. Off-State Instabilities in Thermally Nitrided-Oxide n-MOSFET's. IEEE Trans.Electron Devices 40, 1 (1993), 125-130.

287

MAES, H. E., AND GROESENEKEN, G. Determination of spatial surface state density distribution in MOS and SIMOS transistors after channel hot electron injection. Electron.Lett. 18, 9 (1982), 372-374.

288

MAHNKOPF, R., PRZYREMBEL, G., AND WAGEMANN, H. G. A new method for the determination of the spatial distribution of hot carrier damage. In Proc: ESSDERC (Montpellier (France), 1988), pp. 775-778.

289

MANDURAH, M. M., SARASWAT, K. C., AND HELMS, C. R. Dopant segregation in polycrystalline silicon. J.Appl.Phys. 51, 11 (1980), 5755-5763.

290

MANZINI, S. Effect of Coulomb scattering in -type silicon inversion layers. J.Appl.Phys. 57, 2 (1985), 411-414.

291

MARSHAK, A. H. On the Inappropriate Use of the Intrinsic Level as a Measure of the Electrostatic Potential in Semiconductor Devices. IEEE Electron Device Lett. EDL-6, 3 (1985), 128-129.

292

MARSHAK, A. H., SHIBIB, M. A., FOSSUM, J. G., AND LINDHOLM, F. A. Rigid Band Analysis of Heavily Doped Semiconductor Devices. IEEE Trans.Electron Devices ED-28, 3 (1981), 293-298.

293

MARSHAK, A. H., AND SHRIVASTAVA, R. On threshold and flat-band voltages for MOS devices with polysilicon gate and nonuniformly doped substrate. Solid-State Electronics 26, 4 (1983), 361-364.

294

MARSHAK, A. H., AND VAN VLIET, C. M. Electrical Current and Carrier Density in Degenerate Materials with Nonuniform Band Structure. Proc.IEEE 72, 2 (1984), 148-164.

295

MARSHAK, A. H. On the nonequilibrium carrier density equations for highly doped devices and heterostructures. Solid-State Electronics 31, 10 (1988), 1551-1553.

296

MARSHAK, A. H. Modeling Semiconductor Devices with Position-Dependent Material Parameters. IEEE Trans.Electron Devices 36, 9 (1989), 1764-1772.

297

MARSLAND, J. S. A lucky drift model, including a soft threshold energy, fitted to experimental measurements of ionization coefficients. Solid-State Electronics 30, 1 (1987), 125-132.

298

MARTINEZ, J., AND PIQUERAS, J. On the mobility of polycrystalline semiconductors. Solid-State Electronics 23 (1980), 297-303.

299

MATSUMOTO, H., SAWADA, K., ASAI, S., HIRAYAMA, M., AND NAGASAWA, K. Effect of Long-Term Stress on IGFET Degradations Due to Hot Electron Trapping. IEEE Trans.Electron Devices ED-28, 8 (1981), 923-928.

300

MAZURE, C., SCHWALKE, U., NEPPL, F., EICHINGER, P., AND METZGER, M. Influence of the Fabrication Conditions on the p-TaSi/Poly-Si Gate Quality. In Proc: ESSDERC (Montpellier (France), 1988), pp. 405-408.

301

MAZURÉ, C., SUBRAHMANYAN, R., GUNDERSON, C., AND ORLOWSKI, M. Design considerations for sub- buried channel P-MOSFET devices. In Proc: VLSI Technology Symp. (Seattle (WA), 1992), pp. 92-93.

302

MCAFEE, K. B., RYDER, E. J., SHOCKLEY, W., AND SPARKS, M. Observations of Zener Current in Germanium p-n Junctions. Physical Review 83 (1951), 650-651.

303

MCGILL, T. C. Phenomenology of metal-semiconductor electrical barriers. J.Vac.Sci.Techn. 11, 6 (1974), 935-942.

304

MCLARTY, P. K., IOANNOU, D. E., AND COLINGE, J.-P. Bulk Traps in Ultrathin SIMOX MOSFET's by Current DLTS. IEEE Electron Device Lett. 9, 10 (1988), 545-547.

305

MCMACKEN, J. R. F., AND CHAMBERLAIN, S. G. A Numerical Model for Two-Dimensional Transient Simulation of Amorphous Silicon Thin-Film Transistors. IEEE Trans.Computer-Aided Design 11, 5 (1992), 629-637.

306

MEAD, C. A. Anomalous capacitance of thin dielectric structures. Phys.Review Lett. 6, 10 (1961), 545-546.

307

MERTENS, R. P., VAN MEERBERGEN, J. L., NIJS, J. F., AND VAN OVERSTRAETEN, R. J. Measurement of the Minority-Carrier Transport Parameters in Heavily Doped Silicon. IEEE Trans.Electron Devices ED-27, 5 (1980), 949-955.

308

MII, T., KLEINHENZ, R., NOBLE, W., JOHNSON, J., BRYANT, A., AND JAFFE, M. First Experimental Verification of Collection Length Limited Gate Induced Drain Leakage. In Proc: Int.Electron Devices Meeting (1992), pp. 155-158.

309

MINGAM, H. CMOS Technologies for Logic Applications. In Proc: ESSDERC (Montreux (Swiss), 1991), Elsevier, pp. 243-252.

310

MISTRY, K. R., AND DOYLE, B. AC versus DC Hot-Carrier Degradation in n-Channel MOSFET's. IEEE Trans.Electron Devices 40, 1 (1993), 96-104.

311

MITRINOVIC, D. S., AND KECKIC, J. D. Equations of Mathematical Physics. Gradjevinska knjiga, Belgrade, 1978.

312

MIZUTANI, Y., TAGUCHI, S., NAKAHARA, M., AND TANGO, H. Hot Carrier Instability in Submicron MoSi gate MOS/SOS Devices. In Proc: Int.Electron Devices Meeting (1981), pp. 550-553.

313

MOCK, M. S. A time-dependent numerical model of the insulated-gate field-effect transistor. Solid-State Electronics 24, 10 (1981), 959-966.

314

MOCK, M. S. Analysis of Mathematical Models of Semiconductor Devices. Boole Press, Dublin (Ireland), 1983.

315

MOHAMMAD, S. N. Boundary conditions and current-voltage relations for heavily doped diodes. Solid-State Electronics 30, 7 (1987), 713-718.

316

MOHAMMAD, S. N., AND ROGERS, C. E. Theory of electrical transport and recombination in polycrystalline semiconductors under optical illumination. Solid-State Electronics 31, 7 (1988), 1157-1167.

317

MOHAMMAD, S. N., PATIL, M. B., CHEN, J., ÜNLÜ, M. S., AND MORKOC, H. Analytical model for characteristics of JFETs with heavily doped channels. Solid-State Electronics 33, 1 (1990), 53-64.

318

MOMOSE, H. S., KAMBAYASHI, S., KAWAGUCHI, H., MIZUSHIMA, I., ONGA, S., AND MATSUNAGA, J. A Band-to-Band Tunneling MOSFET Using a Thin Film Transistor. In Proc: Int.Conf. on Solid-State Devices and Materials (Sendai (Japan), 1990), pp. 365-368.

319

MORGAN, T. N. Broadening of Impurity Bands in Heavily Doped Semiconductors. Physical Review 139, 1A (1963), 343-348.

320

MORIMOTO, T., MOMOSE, H. S., IINUMA, T., KUNISHIMA, I., SUGURO, K., OKANO, H., KATAKABE, I., NAKAJIMA, H., TSUCHIAKI, M., ONO, M., KATSUMATA, Y., AND IWAI, H. A NiSi salicide technology for advanced logic devices. In Proc: Int.Electron Devices Meeting (1991), pp. 653-656.

321

MUKAI, M., OHTSU, Y., AND YAGI, A. MOSFET Simulation with B-B Tunnel Current Effect. In Proc: VLSI Process/Device Modeling Workshop, Osaka (Japan) (1989), pp. 56-57.

322

MURAWALA, P. A., SAWAI, M., TATSUTA, T., TSUJI, O., FUJITA, S., AND FUJITA, S. Plasma Enhanced Liquid Source-CVD and Rapid Thermal Annealing of Tantalium Penta Oxide Dielectric Material. In Proc: Int.Conf. on Solid-State Devices and Materials (Tsukuba (Japan), 1992), pp. 527-529.

323

NAKAHARA, M., HIRUTA, Y., NOGUCHI, T., YOSHIDA, M., MAEGUCHI, K., AND KANZAKI, K. Relief of Hot Carrier Constraint on Submicron CMOS Devices by Use of a Buried Channel Structure. In Proc: Int.Electron Devices Meeting (1985), pp. 238-241.

324

NANZ, G., DICKINGER, P., AND SELBERHERR, S. Calculation of Contact Currents in Device Simulation. IEEE Trans.Computer-Aided Design 11, 1 (1992), 128-136.

325

NARITA, K., AND YAMAGUCHI, K. IGFET Hot Electron Emission Model. Solid-State Electronics 23 (1980), 721-725.

326

NEDEV, I., ASENOV, A., AND STEFANOV, E. Experimental study and modeling of band-to-band tunneling leakage current in thin-oxide MOSFETs. Solid-State Electronics 34, 12 (1991), 1401-1408.

327

NEUGROSCHEL, A., PAO, S. C., AND LINDHOLM, F. A. A Method for Determining Energy Gap Narrowing in Highly Doped Semiconductors. IEEE Trans.Electron Devices ED-29, 5 (1982), 894-902.

328

NG, K. K., AND TAYLOR, G. W. Effects of Hot-Carrier Trapping in n- and p-Channel MOSFET's. IEEE Trans.Electron Devices ED-30, 8 (1983), 871-876.

329

NGUYEN-DUC, C., CRISTOLOVEANU, S., AND REIMBOLD, G. Effects of Localized Interface Defects Caused by Hot-Carrier Stress in n-Channel MOSFET's at Low Temperature. IEEE Electron Device Lett. 9, 9 (1988), 479-481.

330

NICOLLIAN, E. H., BERGLUND, C. N., SCHMIDT, P. F., AND ANDREWS, J. M. Electrochemical Charging of Thermal SiO Films by Injected Electron Currents. J.Appl.Phys. 42, 13 (1971), 5654-5664.

331

NICOLLIAN, E. H., AND BREWS, J. R. MOS (Metal Oxide Semiconductor) Physics and Technology. Wiley-Interscience, 1982.

332

NICOLLIAN, E. H. Electrical Characterization of Defects Created in the Si-SiO System by Ionizing Radiation. J.Electronic Materials 21, 7 (1992), 721-729.

333

NILSSON, N. G. Empirical approximations for the Fermi energy in a semiconductor with parabolic bands. Appl.Phys.Lett. 33, 7 (1978), 653-654.

334

NING, T. H., AND YU, H. N. Optically induced injection of hot electrons into SiO. J.Appl.Phys. 45, 12 (1974), 5373-5378.

335

NING, T. H., OSBURN, C. M., AND YU, H. N. Emission probability of hot electrons from silicon into silicon dioxide. J.Appl.Phys. 48, 1 (1977), 286-293.

336

NING, T. H. Hot-Electron Emission from Silicon into Silicon Dioxide. Solid-State Electronics 21 (1978), 273-282.

337

NING, T. H. Thermal reemission of trapped electrons in SiO. J.Appl.Phys. 49, 12 (1978), 5997-6003.

338

NING, T. H., COOK, P. W., DENNARD, R. H., OSBURN, C. M., SCHUSTER, S. E., AND YU, H.-N. 1 MOSFET VLSI Technology: Part IV - Hot-Electron Design Constraints. IEEE Trans.Electron Devices ED-26, 4 (1979), 346-352.

339

NISHINOHARA, K., SHIGYO, N., AND WADA, T. Effects of Microscopic Fluctuations in Dopant Distributions on MOSFET Threshold Voltage. IEEE Trans.Electron Devices 39, 3 (1992), 634-639.

340

NISHIOKA, Y., HOMMA, N., SHINRIKI, H., MUKAI, K., YAMAGUCHI, K., UCHIDA, A., HIGETA, K., AND OGIUE, K. High capacitance ultra-thin TaO dielectric film applied to a high-speed bipolar memory cell. In Proc: Int.Electron Devices Meeting (1985), pp. 42-45.

341

NISHIOKA, Y., SHINRIKI, H., AND MUKAI, K. Influence of SiO at the TaO/Si interface on dielectric characteristics of TaO capacitors. J.Appl.Phys. 61, 6 (1987), 2335-2338.

342

NISHIOKA, Y., KIMURA, S., SHINRIKI, H., AND MUKAI, K. Dielectric Characteristics of Double Layer Structure of Extremely Thin TaO/SiO on Si. J.Electrochem.Soc. 134, 2 (1987), 410-415.

343

NOBLE, W. P., BRYANT, A., AND VOLDMAN, S. H. Parasitic Leakage in DRAM Trench Storage Capacitor Vertical Gated Diodes. In Proc: Int.Electron Devices Meeting (1987), pp. 340-343.

344

NOBLE, W. P., VOLDMAN, S. H., AND BRYANT, A. The Effects of Gate Field on the Leakage Characteristics of Heavily Doped Junctions. IEEE Trans.Electron Devices 36, 4 (1989), 720-726.

345

NYGREN, S., LEVY, D., GOLTZ, G., AND TORRES, J. Dopant Redistribution from Ion Implanted WSi on Poly-Si. In Proc: ESSDERC (Bologna (Italy), 1987), pp. 483-486.

346

NYGREN, S., AMM, D. T., LEVY, D., TORRES, J., GöLTZ, G., D'OUVILLE, T. T., AND DELPECH, P. Dual-Type CMOS Gate Electrodes by Dopant Diffusion from Silicide. IEEE Trans.Electron Devices ED-36, 6 (1989), 1087-1093.

347

ODAKE, Y., KURIMOTO, K., AND ODANAKA, S. Three-Dimensional Numerical Modeling of the Indirect Band-to-Band Tunneling in MOSFET's. In Proc: Int.Conf. on Solid-State Devices and Materials (Sendai (Japan), 1990), pp. 131-134.

348

ODANAKA, S., AND HIROKI, A. A numerical simulation of hot-carrier induced device degradation. In Proc: Int.Conf.VLSI Proc.and Dev. (1991), pp. 108-111.

349

OH, S.-Y., WARD, D. E., AND DUTTON, R. W. Transient Analysis of MOS Transistors. IEEE Trans.Electron Devices ED-27, 8 (1980), 1571-1578.

350

OHATA, A., TORIUMI, A., IWASE, M., AND NATORI, K. Observation of random telegraph signals: Anomalous nature of defects at the Si/SiO interface. J.Appl.Phys. 68, 1 (1990), 200-204.

351

OKAZAKI, Y., KOBAYASHI, T., MATSUDA, T., SAKUMA, K., KAWAI, Y., AND TAKAHASHI, M. A high performance gate CMOS technology. In Proc: VLSI Technology Symp. (Kyoto (Japan), 1989), pp. 13-14.

352

ORLOWSKI, M., MAZURÉ, C., LILL, A., MÜHLHOFF, H.-M., HÄNSCH, W., V. SCHWERIN, A., AND NEPPL, F. Advanced Simulation for Reliability Optimization of Submicron LDD MOSFETs. In Proc: ESSDERC (Berlin (F.R.G.), 1989), pp. 711-714.

353

ORLOWSKI, M., SUN, S. W., BLAKEY, P., AND SUBRAHMANYAN, R. Two-Dimensional Simulation of Band-to-Band Tunneling in an LDD-MOSFET: Explanation of Experimental Results and Prediction of New Phenomena. In Proc: VLSI Technology Symp. (Honolulu (Hawaii), 1990), pp. 67-68.

354

ORLOWSKI, M., SUN, S. W., BLAKEY, P., AND SUBRAHMANYAN, R. The Combined Effects of Band-to-Band Tunneling and Impact Ionization in the Off Regime of an LDD MOSFET. IEEE Electron Device Lett. 11, 12 (1990), 593-595.

355

ORLOWSKI, M. K., AND WERNER, C. Model for the Electric Fields in LDD MOSFET's - Part II: Field Distribution on the Drain Side. IEEE Trans.Electron Devices 36, 2 (1989), 382-391.

356

ORLOWSKI, M. K., WERNER, C., AND KLINK, J. P. Model for the Electric Fields in LDD MOSFET's - Part I: Field Peaks on the Source Side. IEEE Trans.Electron Devices 36, 2 (1989), 375-381.

357

OUISSE, T., CRISTOLOVEANU, S., ELEWA, T., HADDARA, H., BOREL, G., AND IOANNOU, D. E. Adaptation of the Charge Pumping Technique to Gated p-i-n Diodes Fabricated on Silicon on Insulator. IEEE Trans.Electron Devices 38, 6 (1991), 1432-1444.

358

OVERSTRAETEN, R. J. V., DEMAN, H. J., AND MERTENS, R. P. Transport Equations in Heavy Doped Silicon. IEEE Trans.Electron Devices ED-20, 3 (1973), 290-298.

359

OVERSTRAETEN, R. J. V., AND MERTENS, R. P. Heavy doping effects in silicon. Solid-State Electronics 30, 11 (1987), 1077-1087.

360

OZAKI, T., NITAYAMA, A., HAMAMOTO, T., SUNOUCHI, K., AND HORIGUCHI, F. Analysis of Band to Band Tunneling Leakage Current in Trench-Capacitor DRAM Cells. IEEE Electron Device Lett. 12, 3 (1991), 95-97.

361

PARILLO, L. C., WANG, L. K., SWENUMSON, R. D., FIELD, R. L., MELIN, R. C., AND LEVY, R. A. Twin-Tub CMOS II-An Advanced VLSI Technology. In Proc: Int.Electron Devices Meeting (1982), pp. 706-709.

362

PARKE, S., MOON, J., NEE, P., HUANG, J., HU, C., AND KO, P. K. Gate-induced drain leakage in LDD and fully-overlapped LDD MOSFETs. In Proc: VLSI Technology Symp. (Oiso (Japan), 1991), pp. 49-50.

363

PARRILLO, L. C., HILLENIUS, S. J., FIELD, R. L., HU, E. L., FICHTNER, W., AND CHEN, M.-L. A Fine-Line CMOS Technology That Uses P - Polysilicon/Silicide Gates For NMOS and PMOS Devices. In Proc: Int.Electron Devices Meeting (1984), pp. 418-422.

364

PAULSEN, R. E., SIERGIEJ, R. R., FRENCH, M. L., AND WHITE, M. H. Observation of Near-Interface Oxide Traps with the Charge-Pumping Technique. IEEE Electron Device Lett. 13, 12 (1992), 627-629.

365

PETERS, D. Implanted-Silicided Polysilicon Gates for VLSI Transistors. IEEE Trans.Electron Devices ED-33, 9 (1986), 1391-1393.

366

PETKOVIC, D. M. Effects of grain size on completely depleted grains in doped polycrystalline silicon thin films. In Proc: MIEL-87 Int.Conf. (1989), Elsevier Advanced Technology, pp. 209-212.

367

PFIESTER, J. R., AND PARRILLO, L. C. A Novel Dual p/p Poly Gate CMOS VLSI Technology. IEEE Trans.Electron Devices 35, 8 (1988), 1305-1310.

368

PFIESTER, J. R., BAKER, F. K., MELE, T. C., TSENG, H.-H., TOBIN, P. J., HAYDEN, J. D., MILLER, J. W., GUNDERSON, C. D., AND PARRILLO, L. C. The Effects of Boron Penetration on p Polysilicon Gated PMOS Devices. IEEE Trans.Electron Devices ED-37, 8 (1990), 1842-1851.

369

PFIESTER, J. R., MELE, T. C., LIMB, Y., JONES, R. E., WOO, M., BOECK, B., AND GUNDERSON, C. D. A TiN strapped polysilicon gate cobalt salicide CMOS process. In Proc: Int.Electron Devices Meeting (1990), pp. 241-244.

370

PFIESTER, J. R., PARRILLO, L. C., AND BAKER, F. K. A Physical Model for Boron Penetration Through Thin Gate Oxides from p Polysilicon Gates. IEEE Electron Device Lett. 11, 6 (1990), 247-249.

371

PFIESTER, J. R., MELE, T. C., LIMB, Y., JONES, R. E., WOO, M., BOECK, B., AND GUNDERSON, C. D. A Cobalt Salicide CMOS Process with TiN-Strapped Polysilicon Gates. IEEE Electron Device Lett. 12, 6 (1991), 350-352.

372

PIERRET, R. F. The gate-controlled diode measurement and steady-state lateral current flow in deeply depleted MOS structures. Solid-State Electronics 17 (1974), 1257-1269.

373

POLSKY, B. S., AND RIMSHANS, J. S. Half-Implicit Difference Scheme for Numerical Simulation of Transient Processes in Semiconductor Devices. Solid-State Electronics 29, 3 (1986), 321-328.

374

POORTER, T., AND ZOESTBERGEN, P. Hot carrier effects in MOS transistors. In Proc: Int.Electron Devices Meeting (1984), pp. 100-103.

375

POPOVIC, B. Electromagnetics. Gradjevinska knjiga, Belgrade, 1980.

376

PREIER, H. Contributions of surface states to MOS impedance. Appl.Phys.Lett. 10 (1967), 361-363.

377

PRZYREMBEL, G., KRAUTSCHNEIDER, W., SOPPA, W., AND WAGEMANN, H.-G. Interface state analysis of MOSFETs with a modified charge-pumping technique. In Proc: ESSDERC (Bologna (Italy), 1987), pp. 687-690.

378

QUADE, W., RUDAN, M., AND SCH;TEX2HTML_HTML_SPECIAL_MARK_QUOT;OLL, E. Hydrodynamic Simulation of Impact-Ionization Effects in P-N Junctions. IEEE Trans.Computer-Aided Design 10, 10 (1991), 1287-1294.

379

RADOJCIC, R. Some Aspects of Hot-Electron Aging in MOSFET's. IEEE Trans.Electron Devices ED-31, 10 (1984), 1381-1385.

380

RAJAT RAKKHIT, SAMEER HADDAD, C. C., AND YUE, J. Drain-Avalanche Induced Hole Injection and Generation of Interface Traps in Thin Oxide MOS Devices. In Proc: Int. Reliability Physics Symp. (1990), pp. 150-153.

381

RALLS, K. S., SKOCPOL, W. J., JACKEL, L. D., HOWARD, R. E., FETTER, L. A., EPWORTH, R. W., AND TENNANT, D. M. Discrete Resistance Switching in Submicrometer Silicon Inversion Layers: Individual Interface Traps and Low-Frequency (?) Noise. Phys.Review Lett. 52, 3 (1984), 228-231.

382

REDDI, V. G. K., AND SAH, C. T. Source to Drain Resistance Beyond Pinch-Off in Metal-Oxide-Semiconductor Transistors (MOST). IEEE Trans.Electron Devices, 3 (1965), 139-141.

383

REIMBOLD, G. Modified 1/f Trapping Noise Theory and Experiments in MOS Transistors Biased from Weak to Strong Inversion - Influence of Interface States. IEEE Trans.Electron Devices ED-31, 9 (1984), 1190-1198.

384

REVIL, N., CRISTOLOVEANU, S., AND MORTINI, P. Aging study of optimized submicron n-MOSFET's (DC, AC and alternating stress conditions): correlation between charge pumping and classical parameters. In Proc: ESSDERC (Leuven (Belgium), 1992), Elsevier, pp. 461-464.

385

RICCÓ, B., SANGIORGI, E., VENTURI, F., AND LUGLI, P. Monte-Carlo Modeling of Hot Electron Gate Current in MOSFETs. In Proc: Int.Electron Devices Meeting (1986), pp. 559-562.

386

ROBLIN, P., SAMMAN, A., AND BIBYK, S. Simulation of Hot-Electron Trapping and Aging of nMOSFET's. IEEE Trans.Electron Devices 35, 12 (1988), 2229-2237.

387

RODDER, M. Leakage-Current-Induced Hot-Carrier Degradation of p-Channel MOSFET's. IEEE Electron Device Lett. 9, 11 (1988), 573-575.

388

ROSENCHER, E., COPPARD, R., AND BOIS, D. Probing of impurity potential well at the Si/SiO interface by electric-field-enhanced emission. J.Appl.Phys. 57, 8 (1985), 2823-2829.

389

ROUX DIT BUISSON, O., GHIBAUDO, G., AND BRINI, J. Model for drain current RTS amplitude in small-area MOS transistors. Solid-State Electronics 35, 9 (1992), 1273-1276.

390

SAH, C. T. Characteristics of the Metal-Oxide-Semiconductor Transistors. IEEE Trans.Electron Devices, 7 (1965), 324-345.

391

SAH, C. T., AND PAO, H. C. The Effects of Fixed Bulk Charge on the Characteristics of Metal-Oxide-Semiconductor Transistors. IEEE Trans.Electron Devices ED-13, 4 (1966), 393-409.

392

SAH, C. T., NING, T. H., AND TSCHOPP, L. L. The scattering of electrons by surface oxide charges and by lattice vibrations at the silicon-silicon dioxide interface. Surface Science 32 (1972), 561-575.

393

SAI-HALASZ, G. A., WORDEMAN, M. R., KERN, D. P., GANIN, E., RISHTON, S., ZICHERMAN, D. S., SCHMID, H., POLCARI, M. R., NG, H. Y., RESTLE, P. J., CHANG, T. H. P., AND DENNARD, R. H. Design and Experimental Technology for 0.1-m Gate-Length Low-Temperature Operation FET's. IEEE Electron Device Lett. EDL-9, 10 (1987), 463-466.

394

SAI-HALASZ, G. A., WORDEMAN, M. R., KERN, D. P., RISHTON, S., AND GANIN, E. High Transconductance and Velocity Overshoot in NMOS Devices at the 0.1-m Gate-Length Level. IEEE Electron Device Lett. 9, 9 (1988), 464-466.

395

SAKS, N. S., ANCONA, M. G., AND CHEN, W. Interface trap measurements using 3-level charge pumping. In Proc: Int.Conf. on Insulating Films on Semicond. (INFOS) (Liverpool (U.K.), 1991), pp. 139-142.

396

SAKS, N. S., HEREMANS, P. L., DEN HOVE, L. V., MAES, H. E., DE KEERSMAECKER, R. F., AND DECLERCK, G. J. Observation of Hot-Hole Injection in NMOS Transistors Using a Modified Floating-Gate Technique. IEEE Trans.Electron Devices ED-33, 10 (1986), 1529-1533.

397

SAKS, N. S., AND ANCONA, M. G. Determination of Interface Trap Capture Cross Sections Using Three-Level Charge Pumping. IEEE Electron Device Lett. 11, 8 (1990), 339-341.

398

SAKS, N. S., AND ANCONA, M. G. Spatial Uniformity of Interface Trap Distribution in MOSFET's. IEEE Trans.Electron Devices 37, 4 (1990), 1057-1063.

399

SAN, K. T., AND MA, T.-P. Determination of Trapped Oxide Charge in Flash EPROM's and MOSFET's with Thin Oxides. IEEE Electron Device Lett. 13, 8 (1992), 439-441.

400

SANCHEZ, J. J., HSUEH, K. K., AND DEMASSA, T. A. Drain-Engineered Hot-Electron-Resistant Device Structures: A Review. IEEE Trans.Electron Devices 36, 6 (1989), 1125-1132.

401

SANGIORGI, E. Monte Carlo Simulation of Small Silicon Mosfet's. In Proc: Int. Workshop on Computational Electronics (Urbana-Champaign (Illinois), 1992), pp. 37-42.

402

SANO, N., AOKI, T., TOMIZAVA, M., AND YOSHII, A. Electron transport and impact ionization in Si. Physical Review B 41, 17 (1990), 12122-12128.

403

SARASWAT, K. C. Physical and electrical properties of polycrystalline silicon thin films. In Proc: Grain Boundaries in Semiconductors (1982), Elsevier Science Publishing Company, pp. 261-274.

404

SASAKI, H., SAITOH, M., AND HASHIMOTO, K. Hot-carrier induced drain leakage current in n-channel MOSFET. In Proc: Int.Electron Devices Meeting (1987), pp. 726-729.

405

SASAKI, N., NAKANO, M., IWAI, T., AND TOGEI, R. Charge Pumping SOS-MOS Transistor Memory. In Proc: Int.Electron Devices Meeting (1978), pp. 356-359.

406

SASAKI, N., NAKANO, M., AND IWAI, T. Charge Pumping Memory with SOS-MOS Transistors. In Proc: Int.Conf. on Solid-State Devices and Materials (Tokyo (Japan), 1979), pp. 155-160.

407

SASAKI, N. Charge Pumping in SOS-MOS Transistors. IEEE Trans.Electron Devices ED-28, 1 (1981), 48-52.

408

SCHENK, A. Rigorous Theory and Simplified Model of the Band-to-Band Tunneling in Silicon. Solid-State Electronics 36, 1 (1993), 19-34.

409

SCHOKLEY, W., AND JR., W. T. R. Statistics of the Recombinations of Holes and Electrons. Physical Review 87, 5 (1952), 835-842.

410

SCHULZ, M. Modelling of individual interface states in MOSFETs. In Proc: Int.Conf. on Insulating Films on Semicond. (INFOS) (Liverpool (U.K), 1991), pp. 127-130.

411

SCHULZ, M., AND KARMANN, A. Single, Individual Traps in MOSFETs. Physica Scripta T35 (1991), 273-280.

412

SCHWALKE, U., MAZURE, C., AND NEPPL, F. Redistribution of boron implanted into TaSi/poly-Si gates. In Proc: Mat.Res.Soc. Symposium (1988), vol. 106, pp. 187-191.

413

SCHWARZ, S. A., AND RUSSEK, S. E. Semi-Empirical Equations for Electron Velocity in Silicon: Part II - MOS Inversion Layer. IEEE Trans.Electron Devices ED-30, 12 (1983), 1634-1639.

414

SCHWERIN, A., HÄNSCH, W., AND WEBER, W. The Relationship Between Oxide Charge and Device Degradation: A Comparative Study of n- and p-Channel MOSFET's. IEEE Trans.Electron Devices ED-34, 12 (1987), 2493-2500.

415

SELBERHERR, S., SCHÜTZ, A., AND PÖTZL, H. MINIMOS - A Two-Dimensional MOS Transistor Analyzer. IEEE Trans.Electron Devices ED-27 (1980), 1770-1780.

416

SELBERHERR, S. Analysis and Simulation of Semiconductor Devices. Springer Verlag, Wien, New York, 1982.

417

SELBERHERR, S. MOS Device Modeling at 77K. IEEE Trans.Electron Devices 36, 8 (1989), 1464-1474.

418

SELBERHERR, S., HÄNSCH, W., SEAVEY, M., AND SLOTBOOM, J. The Evolution of the MINIMOS Mobility Model. Solid-State Electronics 33, 11 (1990), 1425-1436.

419

SELMI, L., FIEGNA, C., SANGIORGI, E., BEZ, R., AND RICCó, B. Analysis of Uniform Degradation in n-MOSFETs. In Proc: Int.Electron Devices Meeting (1992), pp. 729-732.

420

SELVAKUMAR, C. R. Approximations to Fermi-Dirac Integrals and Their Use in Device Analysis. Proc.IEEE 70, 5 (1982), 516-518.

421

SENGOUGA, N., AND JONES, B. K. Modeling of the Transient Response of Substrate Traps to the Substrate Voltage in GaAs FET's. IEEE Trans.Electron Devices 40, 3 (1993), 471-479.

422

SETO, J. Y. W. The electrical properties of polycrystalline silicon films. J.Appl.Phys. 46, 12 (1975), 5247-5254.

423

SHAW, J.-J., AND WU, K. Determination of spatial distribution of interface states on submicron, lightly doped drain transistors by charge pumping measurement. In Proc: Int.Electron Devices Meeting (1989), pp. 83-86.

424

SHI, Z. M., MIÉVILLE, J.-P., BARRIER, J., AND DUTOIT, M. Low frequency noise and quantum transport in 0.1m N-MOSFET's. In Proc: Int.Electron Devices Meeting (1991), pp. 363-366.

425

SHI, Z. M., MIÉVILLE, J. P., AND DUTOIT, M. Effect of electron heating on RTS in deep submicron n-MOSFET's. In Proc: ESSDERC (Leuven (Belgium), 1992), Elsevier, pp. 751-754.

426

SHIMOYAMA, N., AND TSUCHIYA, T. AC Hot-Carrier-Degradation Mechanism in LDDMOSFET's. In Proc: Int.Conf. on Solid-State Devices and Materials (Tsukuba (Japan), 1992), pp. 518-520.

427

SHINRIKI, H., KISU, T., KIMURA, S.-I., NISHIOKA, Y., KAWAMOTO, Y., AND MUKAI, K. Promising Storage Capacitor Structures with Thin TaO Film for Low-Power High-Density DRAM's. IEEE Trans.Electron Devices 37, 9 (1990), 1939-1947.

428

SHIROTA, R., ENDOH, T., MOMODOMI, M., NAKAYAMA, R., INOUE, S., KIRISAWA, R., AND MASUOKA, F. An accurate model of subbreakdown due to band-to-band tunneling and its application. In Proc: Int.Electron Devices Meeting (1988), pp. 26-29.

429

SHKLOVSKII, B. I., AND EFROS, A. L. Electronic Properties of Doped Semiconductors, vol. 45. Springer-Verlag, 1984. Springer Series in Solid-State Sciences.

430

SHUEY, R. T. Theory of Tunneling Across Semiconductor Junctions. Physical Review 137, 4A (1965), 1268-1277.

431

SIERGIEJ, R. R., YOON, S., AND WHITE, M. H. A New Method of Interface Trap Modeling in Quantized MOSFET Inversion Layers. In Proc: 49th Annual Device Res.Conf. (Univ.of Colorado at Boulder (CO), 1991).

432

SIERGIEJ, R. R., WHITE, M. H., AND SAKS, N. S. Theory and measurement of quantization effects on Si-SiO interface trap modeling. Solid-State Electronics 35, 6 (1992), 843-854.

433

SIMMONS, J. G. Potential barrier attenuation due to electric field penetration of the electrode. Physics Lett. 16, 3 (1965), 233-234.

434

SIMMONS, J. G., AND WEI, L. S. Theory of dynamic charge and capacitance characteristics in MIS systems containing discrete surface traps. Solid-State Electronics 16 (1973), 43-52.

435

SIMMONS, J. G., AND WEI, L. S. Theory of dynamic charge current and capacitance characteristics in MIS systems containing distributed surface traps. Solid-State Electronics 16 (1973), 53-66.

436

SIMOEN, E., DIERICKX, B., AND CLAEYS, C. Random Telegraph Signal Noise: A Probe for Hot-Carrier Degradation Effects in Submicrometer MOSFET's. In Proc: ESSDERC (Leuven (Belgium), 1992), Elsevier, pp. 605-608.

437

SIMOEN, E., DIERICKX, B., CLAEYS, C. L., AND DECLERCK, G. J. Explaining the Amplitude of RTS Noise in Submicrometer MOSFET's. IEEE Trans.Electron Devices 39, 2 (1992), 422-429.

438

SLOTBOOM, J. W., AND DE GRAAFF, H. C. Measurements of bandgap narrowing in Si bipolar transistors. Solid-State Electronics 19 (1976), 857-862.

439

SLOTBOOM, J. W., AND STREUTKER, G. The Mobility Model in MINIMOS. In Proc: ESSDERC (Berlin (F.R.G.), 1989), Springer-Verlag, pp. 87-91.

440

SMITH, G. D. Numerical Solution of Partial Differential Equations. Oxford University Press, London (U.K.), 1965.

441

SNEL, J. The doped Si/SiO interface. Solid-State Electronics 24 (1981), 135-139.

442

SODINI, C. G., EKSTEDT, T. W., AND MOLL, J. L. Charge accumulation and mobility in thin dielectric MOS transistors. Solid-State Electronics 25, 9 (1982), 833-841.

443

SODINI, C. G., KO, P.-K., AND MOLL, J. L. The Effect of High Fields on MOS Device and Circuit Performance. IEEE Trans.Electron Devices ED-31, 10 (1984), 1386-1393.

444

SPECKBACHER, P., ASENOV, A., BOLLU, M., AND KOCH, F. Hot-Carrier-Induced Deep-Level Defects from Gated-Diode Measurements on MOSFET's. IEEE Electron Device Lett. 11, 2 (1990), 95-97.

445

STAHLBUSH, R. E., LAWRENCE, R. K., AND RICHARDS, W. Geometric Components of Charge Pumping Current in SOS Devices. IEEE Trans.Nuclear Science 36, 6 (1989), 1998-2005.

446

STIÉVENARD, D., LANNOO, M., AND BOURGOIN, J. C. Transient capacitance spectroscopy in heavily compensated semiconductors. Solid-State Electronics 28, 5 (1985), 485-492.

447

STIVERS, A. R., AND SAH, C. T. A study of oxide traps and interface states of the silicon-silicon dioxide interface. J.Appl.Phys. 51, 12 (1980), 6292-6304.

448

SUBRAHMANYAN, R. Measurement of two-dimensional doping profiles. In Proc: ESSDERC (Leuven (Belgium), 1992), pp. 585-592. (invited)

449

SUN, J. Y.-C., ANGELUCCI, R., WONG, C. Y., SCILLA, G., AND LANDI, E. Rapid thermal processing of arsenic-implanted polysilicon on very thin oxide. In Proc: ESSDERC (Montpellier (France), 1988), pp. 401-404.

450

SUN, J. Y.-C., WONG, C., TAUR, Y., AND HSU, C.-H. Study of Boron Penetration Through Thin Oxide with P-Polysilicon Gate. In Proc: VLSI Technology Symp. (Kyoto (Japan), 1989), pp. 17-18.

451

SUN, S. C., AND PLUMMER, J. D. Electron Mobility in Inversion and Accumulation Layers on Thermally Oxidized Silicon Surfaces. IEEE Trans.Electron Devices ED-27, 8 (1980), 1497-1508.

452

SUñé, J., OLIVO, P., AND RICCò, B. Self-consistent solution of the Poisson and Schrödinger equations in accumulated semiconductor-insulator interfaces. J.Appl.Phys. 70, 1 (1991), 337-345.

453

SUñé, J., OLIVO, P., AND RICCÒ, B. Quantum-Mechanical Modeling of Accumulation Layers in MOS Structure. IEEE Trans.Electron Devices 39, 7 (1992), 1732-1739.

454

SUNG, J. M., LU, C. Y., CHEN, M. L., HILLENIUS, S. J., LINDENBERGER, W. S., MANCHANDA, L., SMITH, T. E., AND WANG, S. J. Fluorine Effect on Boron Diffusion of P+ Gate Devices. In Proc: Int.Electron Devices Meeting (1989), pp. 447-450.

455

TADA, Y., NAGATA, C., AND IWAHASHI, M. Band-to-Band Tunneling Current as a Probe for the Hot-Carrier Effects. In Proc: Int.Conf. on Solid-State Devices and Materials (Sendai (Japan), 1990), pp. 315-318.

456

TAKAYANAGI, M., IWABUCHI, S., KOBORI, T., AND WADA, T. A new band-to-band tunneling model for accurate device simulations of Si MOSFETs. In Proc: Int.Electron Devices Meeting (1989), pp. 311-314.

457

TAKAYANAGI, M., AND IWABUCHI, S. Theory of Band-to-Band Tunneling Under Nonuniform Electric Fields for Subbreakdown Leakage Currents. IEEE Trans.Electron Devices 38, 6 (1991), 1425-1431.

458

TAKEDA, E., NAKAGOME, Y., KUME, H., AND ASAI, S. New hot-carrier injection and device degradation in submicron MOSFETs. IEE Proc.PartI 130, 3 (1983), 144-149.

459

TAKEDA, E., AND SUZUKI, N. An Empirical Model for Device Degradation Due to Hot-Carrier Injection. IEEE Electron Device Lett. EDL-4, 4 (1983), 111-113.

460

TAKEDA, E., MATSUOKA, H., IGURA, Y., AND ASAI, S. A Band to Band Tunneling MOS Device (BT-MOSFET) - A kind of ``Si Quantum Device'' -. In Proc: Int.Electron Devices Meeting (1988), pp. 402-405.

461

TAKEDA, E., KUME, H., TOYABE, T., AND ASAI, S. Submicrometer MOSFET Structure for Minimizing Hot-Carrier Generation. IEEE Trans.Electron Devices ED-29, 4 (1982), 611-618.

462

TAM, S., HSU, F.-C., HU, C., MULLER, R. S., AND KO, P. K. Hot-Electron Currents in Very Short Channel MOSFET's. IEEE Electron Device Lett. EDL-4, 7 (1983), 249-251.

463

TAM, S., KO, P.-K., HU, C., AND MULLER, R. S. Correlation Between Substrate and Gate Currents in MOSFET's. IEEE Trans.Electron Devices ED-29, 11 (1982), 1740-1744.

464

TAM, S., KO, P.-K., AND HU, C. Lucky-Electron Model of Channel Hot-Electron Injection in MOSFET's. IEEE Trans.Electron Devices ED-31, 9 (1984), 1116-1125.

465

TANAKA, S., AND WATANABE, S. A Model for the Relation Between Substrate and Gate Currents in n-Channel MOSFET's. IEEE Trans.Electron Devices ED-30, 6 (1983), 668-675.

466

TANAKA, S., SAITO, S., ATSUMI, S., AND YOSHIKAWA, K. A Self-Consistent Pseudo-Two-Dimensional Model for Hot-Electron Current in MOST's. IEEE Trans.Electron Devices ED-33, 6 (1986), 743-753.

467

TANAKA, S. A lucky drift model, including a soft threshold energy, for the relation between gate and substrate currents in MOSFET's. Solid-State Electronics 32, 11 (1989), 935-946.

468

TANAKA, T., ISHIUCHI, H., TAKEUCHI, Y., ISHIKAWA, M., MOCHIZUKI, T., AND OZAWA, O. Characterization of MoSi-gate buried channel MOSFET's for a 256K-bit dynamic RAM. In Proc: Int.Electron Devices Meeting (1981), pp. 659-662.

469

TANAKA, T. Shift of the Gate Threshold Voltage of MOS Transistors due to the Introduction of Shallow Impurities. Japan J.Appl.Phys. 10, 1 (1971), 84-91.

470

TANG, D. D. Heavy Doping Effects in p-n-p Bipolar Transistors. IEEE Trans.Electron Devices ED-27, 3 (1980), 563-570.

471

TANIZAWA, M., IKEDA, M., KOTANI, N., AND AKASAKA, Y. An Analytical Model for Band-to-Band Tunneling with Impact Ionization. In Proc: Int.Conf.VLSI Proc.and Dev. (1991), pp. 138-139.

472

TAUR, Y., COHEN, S., WIND, S., LII, T., HSU, C., QUINLAN, D., CHANG, C., BUCHANAN, D., AGNELLO, P., MII, Y., REEVES, C., ACOVIC, A., AND KESAN, V. High Transconductance 0.1m pMOSFET. In Proc: Int.Electron Devices Meeting (1992), pp. 901-904.

473

TAUR, Y., COHEN, S., WIND, S., LII, T., HSU, C., QUINLAN, D., CHANG, C. A., BUCHANAN, D., AGNELLO, P., MII, Y.-J., REEVES, C., ACOVIC, A., AND KESAN, V. Experimental p-Channel MOSFET with p-Polysilicon Gate on 35-ÅGate Oxide. IEEE Electron Device Lett. 14, 6 (1993), 304-306.

474

THOMA, R., PFEIFER, H. J., ENGL, W. L., QUADE, W., BRUNETTI, R., AND JACOBONI, C. An improved impact-ionization model for high-energy electron transport in Si with Monte Carlo simulation. J.Appl.Phys. 69, 4 (1991), 2300-2311.

475

TJAPKIN, D. A. Physical Electronics Solid State. Zavod za izdavanje udzbenika Srbije, Belgrade, 1971.

476

TORIUMI, A., MIZUNO, T., IWASE, M., TAKAHASHI, M., NIIYAMA, H., FUKUMOTO, M., INABA, S., MORI, I., AND YOSHIMI, M. High Speed 0.1 m CMOS Devices Operating at Room Temperature. In Proc: Int.Conf. on Solid-State Devices and Materials (Tsukuba (Japan), 1992), pp. 487-489.

477

TORIUMI, A. Experimental Study of Hot Carriers in Small Size Si-MOSFETs. Solid-State Electronics 32, 12 (1989), 1519-1525. (special issue on hot-carrier transport)

478

TOYOSHIMA, Y., IWAI, H., MATSUOKA, F., HAYASHIDA, H., MAEGUCHI, K., AND KANZAKI, K. Analysis on Gate-Oxide Thickness Dependence of Hot-Carrier-Induced Degradation in Thin-Gate Oxide nMOSFET's. IEEE Trans.Electron Devices 37, 6 (1990), 1496-1503.

479

TSENG, W. L. A new charge pumping method of measuring Si-SiO interface states. J.Appl.Phys. 62, 2 (1987), 591-599.

480

TSUCHIAKI, M., MOMOSE, H. S., MORIMOTO, T., AND IWAI, H. New charge pumping method for direct measurement of spatial distribution of fixed charge. In Proc: VLSI Technology Symp. (1991), pp. 19-20.

481

TSUCHIYA, T., KOBAYASHI, T., AND NAKAJIMA, S. Hot-Carrier-Injected Oxide Region and Hot-Electron Trapping as the Main Cause in Si nMOSFET Degradation. IEEE Trans.Electron Devices ED-34, 2 (1987), 386-391.

482

TSUCHIYA, T. A new enhanced degradation phenomenon in MOSFETs under AC stress: The effect of band-to-band tunneling. In Proc: VLSI Technology Symp. (Kyoto (Japan), 1989), pp. 79-80.

483

UREN, M. J., DAY, D. J., AND KIRTON, M. J. and random telegraph noise in silicon metal-oxide-semiconductor field-effect transistors. Appl.Phys.Lett. 47, 11 (1985), 1195-1197.

484

V. SCHWERIN, A., AND HEYNS, M. M. Investigation on the oxide field dependence of hole trapping and interface state generation in SiO layers using homogeneous nonavalanche injection of holes. J.Appl.Phys. 67, 12 (1990), 7595-7601.

485

V. SCHWERIN, A., BERGNER, W., AND JACOBS, H. Self-Consistent Simulation of Hot-Carrier Damage Enhanced Gate Induced Drain Leakage. In Proc: Int.Electron Devices Meeting (1992), pp. 543-546.

486

VAN DORT, M. J., WOERLEE, P. H., WALKER, A. J., JUFFERMANS, C. A. H., AND LIFKA, H. Influence of High Substrate Doping Levels on the Threshold Voltage and the Mobility of Deep-Submicrometer MOSFET's. IEEE Trans.Electron Devices 39, 4 (1992), 932-938.

487

VAN OVERSTRAETEN, R. J., DECLERCK, G., AND BROUX, G. L. Inadequacy of the Classical Theory of the MOS Transistor Operating in Weak Inversion. IEEE Trans.Electron Devices ED-20, 12 (1973), 1150-1153.

488

VAN OVERSTRAETEN, R. J., DECLERCK, G., AND BROUX, G. L. The Influence of Surface Potential Fluctuations on the Operation of the MOS Transistor in Weak Inversion. IEEE Trans.Electron Devices ED-20, 12 (1973), 1154-1158.

489

VERWEY, J. F., HERINGA, A., DE WERDT, R., AND V.D. HOFSTAD, W. Drift of the breakdown voltage in junctions in silicon (walk-out). Solid-State Electronics 20 (1977), 689-695.

490

VERWEY, J. F., AND DE MAAGT, B. J. Emitter Avalanche Currents in Gated Transistors. IEEE Trans.Electron Devices ED-19, 2 (1972), 245-250.

491

VOLDMAN, S. H., JOHNSON, J. B., LINTON, T. D., AND TITCOMB, S. L. Unified Generation Model with Donor and Acceptor-Type Trap States for Heavily Doped Silicon. In Proc: Int.Electron Devices Meeting (1990), pp. 349-352.

492

VUILLAUME, D., MARCHETAUX, J. C., AND BOUDOU, A. Evidence of Acceptor-Like Oxide Defects Created by Hot-Carrier Injection in n-MOSFET's: A Charge-Pumping Study. IEEE Electron Device Lett. 12, 2 (1991), 60-62.

493

VUILLAUME, D., AND DOYLE, B. S. Properties of hot carrier induced traps in MOSFETs characterized by the floating-gate technique. Solid-State Electronics 35, 8 (1992), 1099-1107.

494

WACHNIK, R. A., AND LOWNEY, J. R. A model for the charge-pumping current based on small rectangular voltage pulses. Solid-State Electronics 29, 4 (1986), 447-460.

495

WACHNIK, R. A. The Use of Charge Pumping to Characterize Generation by Interface Traps. IEEE Trans.Electron Devices ED-33, 7 (1986), 1054-1061.

496

WADA, M., SHIBATA, T., KONAKA, M., IIZUKA, H., AND DANG, R. L. M. A Two-Dimensional Computer Simulation of Hot Carrier Effects in MOSFETs. In Proc: Int.Electron Devices Meeting (1981), pp. 223-226.

497

WALKER, A. J., AND WOERLEE, P. H. The Use of Boron Doped Polysilicon in PMOS Devices. In Proc: ESSDERC (Berlin (F.R.G.), 1989), Springer-Verlag, pp. 29-32.

498

WANG, K. L., AND EVWARAYE, A. O. Determination of interface and bulk-trap states of IGFET's using deep-level transient spectroscopy. J.Appl.Phys. 47, 10 (1976), 4574-4577.

499

WANG, Q., KRAUTSCHNEIDER, W. H., BROX, M., AND WEBER, W. Time dependence of hot-carrier degradation in LDD nMOSFETs. In Proc: ESSDERC (Montreux (Swiss), 1991), Elsevier, pp. 441-444.

500

WANG, Q., BROX, M., KRAUTSCHNEIDER, W. H., AND WEBER, W. Explanation and Model for the Logarithmic Time Dependence of p-MOSFET Degradation. IEEE Electron Device Lett. 12, 5 (1991), 218-220.

501

WANG, S. J., CHEN, I.-C., AND TIGELAAR, H. L. Effects of Poly Depletion on the Estimate of Thin Dielectric Lifetime. IEEE Electron Device Lett. 12, 11 (1991), 617-619.

502

WANG, X. L., CHANDRAMOULI, V., MAZIAR, C. M., AND TASCH, A. F. An efficient Multi-Band Monte Carlo Model with Anisotropic Impact Ionization. In Proc: Int.Electron Devices Meeting (1992), pp. 725-728.

503

WATANABE, D. S., AND SLAMET, S. Numerical simulation of hot-electron phenomena. SIAM J.Sci.Stat.Comput. 4, 3 (1983), 436-451.

504

WATT, J. T. Modeling the Performance of Liquid-Nitrogen Cooled CMOS VLSI. Tech. rep., Integrated Circuits Laboratory, Stanford University, Stanford (CA), 1989. No. G725-3.

505

WIEDER, A. W. Arsenic emitter effects. In Proc: Int.Electron Devices Meeting (1978), pp. 460-462.

506

WIKSTROM, J. A., VISWANATHAN, C. R., AND ABIDI, A. A. Microscopic Mobility of Electrons in Weakly Inverted MOSFETs. In Proc: Int.Electron Devices Meeting (1987), pp. 648-651.

507

WILLIAMS, C. K. Kinetics of Trapping, Detrapping, and Trap Generation. J.Electronic Materials 21, 7 (1992), 711-720.

508

WITCZAK, S. C., SUEHLE, J. S., AND GAITAN, M. An experimental comparison of measurement techniques to extract Si-SiO interface trap density. Solid-State Electronics 35, 3 (1992), 345-355.

509

WITTERS, J. S., GROESENEKEN, G., AND MAES, H. E. Degradation phenomena of tunnel oxide floating gate EEPROM devices. In Proc: ESSDERC (Bologna (Italy), 1987), pp. 167-170.

510

WITTERS, J. S., GROESENEKEN, G., AND MAES, H. E. Programming mode dependent degradation of tunnel oxide floating gate devices. In Proc: Int.Electron Devices Meeting (1987), pp. 544-547.

511

WOLBERT, P., VAN SCHIE, E., WIJBURG, R., HEMINK, G., AND MIDDELHOEK, J. Simulation of novel EPROM structure using the energy-balance equations. In Proc: NUPAD Conf. (Honolulu (Hawaii), 1990), pp. 51-52.

512

WONG, C. Y., SUN, J. Y.-C., TAUR, Y., OH, C. S., ANGELUCCI, R., AND DAVARI, B. Doping of N and P Polysilicon in a Dual-Gate CMOS Process. In Proc: Int.Electron Devices Meeting (1988), pp. 238-241.

513

WONG, M., AND SARASWAT, K. C. Direct Tungsten and Tungsten Shunted Polysilicon Gate Submicron CMOS Technology. In Proc: VLSI Technology Symp. (Kyoto (Japan), 1989), pp. 101-102.

514

WORDEMAN, M. R. Characterization of depletion mode MOSFETs. In Proc: Int.Electron Devices Meeting (1979), pp. 26-29.

515

WOUTERS, D. J., TACK, M. R., GROESENEKEN, G. V., MAES, H. E., AND CLAEYS, C. L. Characterization of Front and Back Si-SiO Interfaces in Thick- and Thin-Film Silicon-on-Insulator MOS Structures by the Charge-Pumping Technique. IEEE Trans.Electron Devices 36, 9 (1989), 1746-1750.

516

WU, C.-Y., AND KEN, W.-D. A new computer-aided simulation model for polycrystalline silicon film resistors. Solid-State Electronics 26, 7 (1983), 675-684.

517

YANG, P. C., CHEN, H. S., AND LI, S. S. Measurements of interface state density in partially- and fully-depleted silicon-on-insulator MOSFETs by a high-low-frequency transconductance method. Solid-State Electronics 35, 8 (1992), 1031-1035.

518

YANG, R. Q., SWEENY, M., DAY, D., AND XU, J. M. Interband Tunneling in Heterostructure Tunnel Diodes. IEEE Trans.Electron Devices 38, 3 (1991), 442-446.

519

YANO, H., KUMASHIRO, S., GOTO, N., AND OHNO, Y. Two dimensional transient device simulator with deep trap model for compound semiconductor devices. In Proc: Int.Electron Devices Meeting (1989), pp. 151-154.

520

YARON, G., AND FROHMAN-BENTCHKOWSKY, D. Capacitance voltage characterization of poly Si-SiO-Si structures. Solid-State Electronics 23 (1980), 433-439.

521

YASUDA, N., NAKAMURA, H., TANIGUCHI, K., AND HAMAGUCHI, C. Interface state generation mechanism in N-MOSFETs. Solid-State Electronics 32, 12 (1989), 1579-1583.

522

YOSHIKAWA, K., MORI, S., SAKAGAMI, E., OHSHIMA, Y., KANEKO, Y., AND ARAI, N. Lucky-Hole Injection Induced by Band-to-Band Tunneling Leakage in Stacked Gate Transistors. In Proc: Int.Electron Devices Meeting (1990), pp. 577-580.

523

YOUNG, D. R. Electron current injected into SiO from p-type Si depletion regions. J.Appl.Phys. 47, 5 (1976), 2098-2102.

524

YOUNG, D. R., IRENE, E. A., DIMARIA, D. J., AND KEERSMAECKER, R. F. D. Electron trapping in SiO at 295 and 77K. J.Appl.Phys. 50, 10 (1979), 6366-6372.

525

ZENER, C. A Theory of the Electrical Breakdown of Solid Dielectrics. Proc.Roy.Society A145 (1934), 523-529.