BTI – Causes and Impacts

1.2 BTI – Causes and Impacts

The focus of this thesis lies on the advanced characterization of the bias temperature instability and the interpretation of performed stress and relaxation measurements. To be able to understand how BTI affects the MOS-structure, the phenonmenon has to be specified first.

BTI happens when the gate of a heated MOSFET is heavily biased while keeping the other contacts grounded [6, 7]. Under these conditions the threshold voltage $VTH$ , the channel mobility $μchan$ , the transconductance $gm$ or subthreshold slope, amongst other transistor parameters were shown to degrade.

The most prominent form of BTI when dealing with modern CMOS technologies occurs when the gate of a pMOSFET is biased negatively (in the strong inversion regime); this is called NBTI. When the gate is biased positively, the phenomenon is called PBTI. Including the nMOSFET there are four different permutations of BTI to be distinguished: NBTI/pMOS, PBTI/pMOS, NBTI/nMOS, PBTI/nMOS. Besides the already mentioned case of NBTI/pMOS which exhibits the most dominant effect within the BTI-family, also nMOSFETs show non-negligible PBTI behavior, especially when using high- $κ$ dielectrics. The remaining PBTI/pMOS and NBTI/nMOS combinations are less prone to degrade due to BTI.

As a consequence of BTI, the overall change of the degrading parameters increases the probability that the device fails to meet the specification requirements [8, 9], which may yield a malfunctioning device (though not necessarily destroyed yet). Therefore BTI is of industrial as well as scientific interest.

Although silicon as bulk material is a very good heat dissipator to cool the active area inside the MOSFET, the down-scaling mentioned in Chapter 1.1 leads to increasing operation temperatures inside the devices. This increasing operation temperatures slowly move towards the typical NBTI stress temperature ranging between room temperature and $200∘C$ . Due to the increased thermal budget the use conditions for MOSFETs become more demanding.

Unfortunately, at some point during miniaturization the validity of the ideal scaling rule [2] was limited by other factors [10]: Since the on/off current ratio of the MOSFET has to be large enough to be able to distinguish between the signal, the threshold voltage must not be reduced too much. Also, the gate oxide thickness is limited to at least a few atomic layers ( $≈ 1nm$ ). These two limitations violate the condition that the oxide electric field $Eox$ remains constant when scaling further; the typically occuring $E ox$ during the operation a MOSFET starts to increase and NBTI becomes more important. Also, tunneling through the oxide and other quantum-mechanical effects become relevant.

During BTI stress the oxide electric field $Eox$ is nearly homogeneous along the channel and thus the description of $Eox$ can be reduced to the vertical oxide electric field $Eoxver$ ranging between $± 4MV ∕cm$ up to $± 8MV ∕cm$ and being perpendicular to the interface between oxide and substrate.

When adding a lateral field $Eoxlat$ by also applying a voltage between source and drain, the carrier velocity in the channel at the drain side increases rapidly. The resulting hot carrier injection (HCI) is supposed to be related to the BTI phenomenon, at least to some extent, but even more complex because of the two electric field components adding up. Hence, a profound knowledge of BTI is required to also understand HCI.

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