10.2 Topography Simulation and Motivation

The resolution achieved by lithography determines the minimum size - also called critical dimension - of the features of an integrated circuit and hence is a decisive property of the manufacturing process. For CMOS integrated circuits the critical dimension is the gate length, and process technologies are denoted by their critical dimensions, e.g., $250\,\mathrm{nm}$, $180\,\mathrm{nm}$, $130\,\mathrm{nm}$, $100\,\mathrm{nm}$, and $70\,\mathrm{nm}$. While lithography is a major factor in process technology, other aspects are becoming more and more important. Integration does not only proceed in horizontal direction, but it is being expanded vertically. An example of this development for achieving higher integration are deep trench capacitors for small area DRAM (dynamic random access memory) cells.

Etching and deposition processes go hand in hand with lithography, since after transferring the pattern to the photo resist on the wafer, the features must be etched with high directionality downwards into the substrate, layers have to be deposited, and trenches have to be filled without voids. Ensuring good quality of the resulting components becomes more and more demanding as scaling continues. Also when developing new deposition and etching techniques, certain minimum deposition and etching rates have to be achieved to ensure that the processes are applicable in an industry setting, where manufacturing throughput has to be considered.

Furthermore the processes are required to work uniformly across the wafer. For wafer sizes of eight and twelve inches ensuring the uniformity poses nontrivial problems. Here simulations contribute to achieving the required yield and quality of all features on the wafer by estimating the variation in the profiles at different positions.

New etching technologies for accurately transferring patterns into the substrate prompted new, more advanced design rules. At the same time the size of the contacts has been shrinking and complex interconnect schemes with several metal layers have been introduced, which require void-less contacts and barrier layers free of leakage.

Precise knowledge of the actual chemical surface reactions that occur during plasma etching or CVD processes is usually not available. The question of finding the predominant species, their reactions, and the reaction coefficients cannot be answered by any general chemical theory and hence must be considered on a single case base. Here simulations provide crucial input to understanding the importance and influence of single reactions and their effects on the whole topography process and help devise and test new theories. The problem of the precise nature of the chemical surface reaction can also be viewed as an inverse modeling problem, and hence it can be attacked by the means developed in this thesis. This is again an illustration of the fundamental relationship between reality and simulation depicted in Figure 6.2.

In order to determine the actual processes on the molecular level and their reaction coefficients rigorously, a large number of quantum chemical simulations would be required. It can be expected that the computational resources needed for these investigations will be available in the next decade, but this kind of simulation does not lie within the scope of this thesis.

All these considerations underline the importance of topography simulation, i.e., the change of the shape of the wafer substrate or layers thereon during manufacturing processes. For rigorous simulations many physical and chemical processes must be modeled and coupled to a precise and robust means of describing the time evolution of surfaces. In the second part topography simulation requests by industrial partners are considered.