12.8 Simulation of Void Formation during Backend Processes

**Figure 12.5:** SEM image of a test structure with trenches of different widths. This detail shows metal 2 and 3 layers of the interconnect structure of a memory cell. In the upper row (M3 layer) the trenches are about 0.45 micrometer wide and a nitride film was deposited. In the lower row (M2 layer) silicon dioxide was deposited from TEOS.
$\includegraphics[width=0.45\linewidth]{figures/fib-figure-28-detail1}$

**Figure 12.6:** Simulation of void formation as shown in Figure 12.5. Here a level set grid of $80\cdot 160$ points was used and the coarsening algorithm was applied twice, substituting at most four neighboring surface elements by a new one.
$\includegraphics[height=10cm]{figures/cypress-test-1-0090}$

**Figure 12.7:** The figures show the intermediate level set grids at steps 10, 20, 30, 40, 50, 60, 70, 80, and 90 during the simulation in Figure 12.6. In the narrow band the signed distance function is retained until the end of the simulation, whereas other points have not been touched after the initialization. The flat area remains after being touched by the moving narrow band.
Step 10. $\includegraphics[width=0.32\linewidth]{figures/cypress-test-1-ls-0010}$ Step 20. $\includegraphics[width=0.32\linewidth]{figures/cypress-test-1-ls-0020}$ Step 30. $\includegraphics[width=0.32\linewidth]{figures/cypress-test-1-ls-0030}$ Step 40. $\includegraphics[width=0.32\linewidth]{figures/cypress-test-1-ls-0040}$ Step 50. $\includegraphics[width=0.32\linewidth]{figures/cypress-test-1-ls-0050}$ Step 60. $\includegraphics[width=0.32\linewidth]{figures/cypress-test-1-ls-0060}$ Step 70. $\includegraphics[width=0.32\linewidth]{figures/cypress-test-1-ls-0070}$ Step 80. $\includegraphics[width=0.32\linewidth]{figures/cypress-test-1-ls-0080}$ Step 90. $\includegraphics[width=0.32\linewidth]{figures/cypress-test-1-ls-0090}$

In backend processes for memory cells ILD (interlevel dielectric) materials and processes result in void formation during gap fill. This approach lowers the overall

-value of a given metal layer and is economically advantageous. The impact of the voids on the total capacitive load is tremendous.

In order to provide predictive simulations of the overall capacitance, the shape and positions of the voids must be simulated accurately. Then topography simulations can serve as input to capacitance extraction.

Test structures of interconnect lines of memory cells were fabricated by an industrial partner, and several SEM images thereof were used to validate the corresponding simulations. For metal lines 1 and 2 the deposition of silicon dioxide films from TEOS was considered and for metal line 3 the deposition of silicon nitride was simulated. The detail in Figure 12.5 shows metal 2 and 3 layers. The test structures contain trenches of different widths and the influence of the width is precisely reproduced in the simulations. An example of void formation after silicon nitride deposition (cf. Section 12.6) is shown in Figure 12.5 and Figure 12.6. Figure 12.7 shows the corresponding level set function. The shape and position of the void is reproduced correctly in the simulation.