2.1 Applications of Three-Dimensional Device Simulation

Three-dimensional device simulation is mandatory for investigations on real three-dimensional structures because these structures cannot be described by two-dimensional cuts. As an example, Fig. 2.1 shows the three-dimensional structure of a Lateral Trench LDMOSFET. The figure shows the device at breakdown with $V_{GD} = V_{GD} = 90V$ . The gate is built by a trench whereas the channel forms at the sidewall of the trench gate vertically in the device. Due to the super-junction concept the drift area is fully depleted at breakdown. The potential is uniformly distributed to account for the Reduced Surface Field (RESURF) effect.

**Figure 2.1:** Potential distribution [V] and iso-lines of an example Lateral Trench LDMOSFET at breakdown.
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Furthermore, three-dimensional simulations are mandatory when feature sizes become so small that the three-dimensional shape of geometries cannot be neglected. Thus two-dimensional simulations are no more reliable. A frequently cited example is the narrow channel effect of MOS transistors which are normally simulated in two-dimensional cuts. When the width of the channel becomes comparable to its length, the current path becomes clearly three-dimensional.

Another more obvious example is the temperature profile in real devices. Two-dimensional simulations cannot predict temperature profiles very well, because they do not take all cooling plates and directions of the heat flow into account. As an example Fig. 2.2 shows the geometry of a body contacted SOI MOS transistor. The gate is T-shaped and its length is $0.125\,\mu{\mathrm{m}}$ and the width $1\,\mu{\mathrm{m}}$ . The gate oxide thickness is $2.2\,{\mathrm{nm}}$ . The transistor is surrounded by a rectangular silicon area of $1 {\mu}m$ width which has been used here only to increase the cooling area and therefore to make the resulting temperature profile more visible.

**Figure 2.2:** Body contacted MOS transistor on SOI.
$\begin{figure}\vspace{-0.4cm} \begin{center} \psfig{file=figures/soi/soi_heat_geometry, width=12.5cm} \end{center}\vspace{-1.cm} \end{figure}$

Fig. 2.3 shows the result of a three-dimensional simulation. At the thermal contacts $300\,{\mathrm{K}}$ was applied. The temperature profile is clearly three-dimensional contrary to the assumptions made for two-dimensional simulations. At the end of the gate in

-direction the temperature is $5.1\,{\mathrm{K}}$ lower than in the middle.

**Figure 2.3:** Iso-surfaces of the temperature profile [K] of the body contacted SOI MOS transistor shown in Fig. 2.2.
$\begin{figure}\vspace{0.4cm} \begin{center} \psfig{file=figures/soi/soi_heat_3D_1um, width=12.5cm} \end{center}\vspace{-0.4cm} \end{figure}$

Fig. 2.4(a) shows the result of a two-dimensional simulation performed for the cut A-A depicted in Fig. 2.2. As a comparison, in Fig. 2.4(b) the same cut A-A is shown for the three-dimensional simulation of Fig. 2.3. As expected, the highest temperature appears in the channel below the gate and decreases with increasing lateral distance to the channel. Because the thermal resistance of SiO2 is much higher than that of silicon, a high temperature range is supplied by the gate.

Figure 2.4: Temperature profiles [K] in cut A-A of a two- and a three-dimensional simulation.

$\psfig{file=figures/soi/soi_heat_2D_rot,width=12cm}$

(a) Two-dimensional simulation.

$\psfig{file=figures/soi/soi_heat_3D_cut_rot,width=12cm}$

(b) Three-dimensional simulation.

To clearly stress out this result the temperature at the surface of the silicon segment of both the two-dimensional simulation ( Fig. 2.4(a)) and the cut of the three-dimensional result (Fig. 2.4(b)) is shown in Fig. 2.5. It can be clearly seen, that the two-dimensional simulation predicts a much higher temperature compared to the three-dimensional one. The maximal temperature in the channel below the gate is calculated as $322.5\,{\mathrm{K}}$ for the two-dimensional case and as $314.7\,{\mathrm{K}}$ for the three-dimensional case. Therefore, the error of the temperature increase due to self heating made by the two-dimensional simulation is about $53\%$ below the gate and about $133\%$ at the side.

**Figure 2.5:** Surface temperature [K] of the simulation result shown in Fig. 2.4.
$\begin{figure}\vspace{0.4cm} \begin{center} \psfig{file=figures/soi/soi_heat_cut_xcrv_rot, width=11.5cm} \end{center}\vspace{-0.4cm} \end{figure}$

Fig. 2.6 and Fig. 2.7 show the temperature profile of a body contacted SOI MOS transistor with a gate width of $0.5\,\mu{\mathrm{m}}$ and $2\,\mu{\mathrm{m}}$ , respectively. Both figures show a three-dimensional shape of the temperature inside the device. But from these figures one can clearly see the increasing importance of three-dimensional simulations with decreasing feature sizes of the devices. Two-dimensional simulations are no more accurate enough, not even for long devices.

**Figure 2.6:** Temperature profile [K] of the body contacted SOI MOS transistor shown in Fig. 2.2 with a gate width of $0.5 {\mu }m$ .
$\begin{figure}\vspace{0.4cm} \begin{center} \psfig{file=figures/soi/soi_heat_3D_05um, width=12.5cm} \end{center}\vspace{-0.4cm} \end{figure}$

**Figure 2.7:** Temperature profile [K] of the body contacted SOI MOS transistor shown in Fig. 2.2 with a gate width of $2 {\mu }m$ .
$\begin{figure}\vspace{0.4cm} \begin{center} \psfig{file=figures/soi/soi_heat_3D_2um, width=12.5cm} \end{center}\vspace{-0.4cm} \end{figure}$