4.1.1 Device Structure and Properties

The structure of a superjunction LDMOSFET (SJ-LDMOSFET) is shown in Fig. 4.1. The whole structure is implemented on p-doped silicon on insulator (SOI) with a p-doping concentration of $3\cdot10^{15}\,{\mathrm{cm}}^{-3}$. The device contains a highly doped source and drain where an additional p$^+$-doping at the source contact is used to avoid leakage current by removing holes in the p-body below the channel where electrons and holes are generated thermally. If no highly doped p$^+$-region would be used the holes would flow to the n$^+$-doped source and electrons would be introduced to the p-body thus turning on parasitic bipolar transistor action.

Figure 4.1: Geometry of the simulated SJ-LDMOSFET structure.

Figure 4.2: Top view of the SJ-LDMOSFET structure.

Superjunctions are formed in the n-drift region of the device by alternating n- and p-doped columns. The structure shown in Fig. 4.1 can be continued regularly in the $z$-direction as shown in Fig. 4.2 where the simulated area is marked. Charge balance of the n- and p-columns is achieved and the columns are fully depleted when the transistor is turned off. The widths of the n- and p-columns are $0.5\,\mu\mathrm{m}$, respectively.

The breakdown voltage is limited by the thickness of the buried oxide and the drift layer length. The device has been designed to achieve a breakdown voltage of $120\,{\mathrm{V}}$. Both, the buried oxide thickness and the SOI thickness, are $1\,\mu\mathrm{m}$.

For the following simulations the shown SJ-LDMOSFET is compared with a device without superjunctions. For this device simple two-dimensional simulations have been applied. Apart from the superjunctions the device geometry is the same as for the SJ-LDMOSFET. For comparison this conventional LDMOSFET device has also been designed to achieve a breakdown voltage of $120\,{\mathrm{V}}$.