4.4 FinFET

Downscaling of the feature sizes of semiconductor devices is one of the main driving forces in the semiconductor industry. According to the ITRS 2001 Roadmap printed gate lengths down to $13\,{\mathrm{nm}}$ are expected for the year $2016$ [7]. In recent years MOSFET devices have been aggressively scaled in combination with a complex design of the channel doping to avoid short channel effects. Further scaling beyond the $0.1\,\mu\mathrm{m}$ process generation will be difficult if not impossible at all due to limitations given by lateral short channel effects and gate insulator tunneling [158,159,160,161]. One approach to avoid gate tunneling is the use of thicker gate oxides of different materials (high-k materials).

Multi-gate MOSFETs have been considered one of the most attractive devices to achieve channel lengths smaller than $20\,{\mathrm{nm}}$. Recently, several structures have been proposed such as delta structures [162,163] which use a thin vertical silicon membrane or gate-all-around structures [164,165] whereby a silicon fin is completely surrounded by a ring-shaped gate. Several improvements and variations have been reported like the Pi-gate MOSFET [166]. In addition, in [167] a five-channel MOSFET has been proposed which actually is a combination of a gate-all-around and a single-gate structure. All approaches have in common that a very thin silicon membrane or fin is surrounded by several gates. To completely control the silicon area between the gates the silicon area must be fully depleted. Short channel effects can be avoided using very thin membranes or fins [168].

The alignment of the gates to each other and to the implanted doping profiles is very crucial for the device performance [169] and constitutes one of the key issues for multi-gate device manufacturing. Therefore, self-aligned processes have been introduced where the FinFET concept is one of the most promising [162,163]. FinFET devices with gate lengths down to $18\,{\mathrm{nm}}$ and a gate oxide thickness of $2.5\,{\mathrm{nm}}$ have been tested experimentally [168].

Most of the reported results describe experiments [170,171,172,173,174,175] or rely on simplified two-dimensional simulations [168,176]. Only few three-dimensional investigations have been performed for FinFET structures [177]. However, such devices are heavily influenced by three-dimensional effects such as gate coupling or corner effects. Three-dimensional simulations are, therefore, mandatory to properly predict the behavior of such devices.