4.1 Causes for Power Consumption in ICs

During operation circuits waste energy. There are three major causes of power dissipation in integrated circuits:

• Dynamic power consumption which is caused by diabatic charging and discharging of (usually parasitic) capacitances;

• Static power consumption which corresponds to the non-zero current of transistors in off state in digital circuits or the biasing current in their analog counterparts; and

• Short-circuit power consumption caused by the crow-bar current flowing during the lapse of time when both PMOS and NMOS transistors are in the on state.

The first item in most cases dominates the power consumption in digital circuits. The dynamic power $P_{dyn}$ of a digital circuit block is given by

$$P_{dyn}=N \cdot C_{eq} \cdot {V_{DD}}^2$$ (4.1)

where $C_{eq}$ is the average load capacitance of internal and load nodes, $V_{DD}$ is the power supply voltage, and $N$ is the average number of transitions necessary to complete an instruction or a task per second. This number depends on the clock frequency and other factors related to architectural decisions, like whether the design is synchronous or not. Synchronous circuits are today the solution for complex digital circuitry [36] as this concept prevents race conditions and other hazards from occuring. But they use clock signals whose long lines globally distributed over the chip are heavily loaded and waste a lot of power without performing any useful logic function. Asynchronous designs where transitions are reduced to a minimum do much better in power consumption. Special design techniques as Double Pass-Transistor Logic CMOS (DPTLCMOS) [37] can also have a better performance than conventional static logic concerning power dissipation. Dynamic and static logic also originate different values for $N$. A study comparing several design styles can be found in [37][38].

The second item depends on the total current of the transistors in the off state $I_{off}$ and equals

$$P_{static}= I_{off} \cdot V_{DD}.$$ (4.2)

For conventional CMOS technologies with high threshold voltages this contribution is diminutive and impacts only the power dissipation in the standby mode. However, in analog and some digital bipolar technologies such as Emitter-Coupled Logic (ECL) it is the main contribution for power dissipation as the devices are biased permanently in their active or saturation modes.

During switching in CMOS, for a short period of time, both NMOS and PMOS are simultaneously active and an instantaneous short-circuit current flows from the power supply directly to ground. The total short circuit current $I_{sc}$ contributes for the power consumption by

$$P_{sc}= I_{sc} \cdot V_{DD}.$$ (4.3)

This item can be neglected if signals have short rise and fall times when compared to the signal's period. As this is usually the case, we will not give more attention to this component. Thus, the total power consumption is, in good approximation, given by the sum of the first two contributions:

$$P_{total} \approx N \cdot C_{eq} \cdot {V_{DD}}^2 + I_{off} \cdot V_{DD}.$$ (4.4)