4. Low Power Strategies

The biggest threat that Moore's law faces, is not triggered by any difficulty in process scaling, but barriers imposed by packaging and cooling. In fact we start to find a power wall [4]. There are several reasons for reaching this stage, and certainly, a design strategy which in the large majority of VLSI-based electronic systems (including most of the computer and telecommunication equipment) put power consumption close to the last priority in the list of specifications had a major role [35].

Figure 4.1: Trends in the power consumption of high-performance ICs.

The design strategies were directed to reach higher speed and larger dynamic range. The associated increase in power consumption from the point of view of normal desktop equipment is irrelevant and the thermal management of the circuits was being solved by bigger packages (which were needed anyway to cope with the increase in the number of I/O pins) and more efficient cooling systems. This trend is expected to grow until the year 2010, approximately (see Figure 4.1 [2]), when it will become almost impossible to remove more heat from the package. However, this predicted limitation and the fact that, already today, the dissipated power is very high, are changing the design philosophy of modern integrated circuits completely, and a more careful modeling of the thermal budget has to be considered.

The development of new technologies for systems applications requires tools able to deal with the growing complexity necessary to achieve high-performance and low-power concurrently. Unfortunately, there are several missing features in classical frameworks to accomplish this task. In this chapter we will refer to the causes for power consumption.