5.2.3 Circuit Simulation

As discussed in Section 4.2.1 a ring oscillator is a good circuit for technology performance evaluation. We use it as benchmark circuit of the previously described technology. In relation to the ring oscillator depicted in Figure 4.2 the first inverter INV$_1$ is replaced by a NAND gate (see the new schematic in Figure 5.14) so there is an extra input pin available that can be used to enable or disable the oscillations: The oscillator only works when the $enable$ input is at logical level ``1''.

Figure 5.14: Schematic of a ring oscillator with enable pin: (i) Logic level. (ii) Transistor level.

The layout corresponding to the schematic of Figure 5.14-(ii) uses typical 0.5$\mu m$ design rules and it is presented in Figure 5.15. To save chip area all PMOS and NMOS transistors lie in the same N-well or P-well, respectively. The feedback line is layed in METAL2 over the transistor.

Figure 5.15: Layout of the ring oscillator.

Before we present the results of this circuit, we want to stress the importance of the possibility of checking the influence of technology parameters in the circuit performance. When the devices are defective due to a wrong fabrication setup, most probably a circuit like the ring oscillator will not work properly, i.e. it will not oscillate, the oscilation amplitude is to low or the frequency is lower than expected. For the initial tests on devices and circuits the inverter (in spite of being the simplest circuit) is a very good choice.

When developing a low-voltage, low-power technology for digital circuit purposes, the most important issue is perhaps to achieve the highest $I_{on}/I_{off}$ current ratio^145#3. This involves a careful investigation of the optimal threshold voltage and proper process parameters control: a too high threshold voltage will reduce $I_{off}$ but also $I_{on}$ and the devices will be very slow. On the other hand, the option for a too low threshold voltage can make $I_{off}$ so large, that a proper operation of the device is not possible.

Figure 5.16: Inverter transient response before and after the optimization of the threshold adjustment implant.

In Figure 5.16 we show the response of an inverter (like the ones in the ring oscillator) for a case before the optimization of the threshold adjustment implant and for the final devices (after optimization). It can be observed that although the inverter operation is still achieved, the output before optimization never reaches the power supply voltage. This behavior could not be tolerated in a circuit, as the noise margins are seriously reduced, even if its speed is a little faster than in the optimized case. The problem was related to the too low value of the NMOS threshold voltage that originated a large leakage current which, associated to a relative low drive current of the PMOS transistor, forced the output voltage to be somewhat below the upper power supply rail. Even if $I_{on}$ of the PMOS transistor were enough, the circuit would have an unacceptable high static power consumption. After optimization, we end up with the device characteristics shown in Table 5.1. The threshold voltages as usually defined for transistors working in strong inversion do not apply to these low-voltage technologies. The threshold values reported in the following table are defined as the gate-source voltage (with bulk and source connected) that satisfy (5.1) [50].

$$\left\vert I_{drain} \right\vert = 1~\mu A / \mu m.$$ (5.1)

Table 5.1: Low-voltage, low-power technology device characteristics.

	PMOS	NMOS
$V_{DD}$  (nominal)	0.5 V	0.5 V
$V_{Th}$	0.25 V	0.25 V
$I_{on}$	16.5 $\mu A~~~~~~~$	25.5 $\mu A$
$I_{off}$	2.8 $nA$	0.7 $nA$

Figure 5.17: Ring oscillator transient simulation.

The result from the ring oscillator transient simulation is shown in Figure 5.17. The delay as given by (4.7) is 0.275$ns$ corresponding to an oscillation frequency of 365MHz. In fact, there is a small inaccuracy in using (4.7) because the delay time in the NAND gate is slightly larger than in the inverters (about 7.5%). This happens due to the reduced transconductance of the series connected NMOS transistors (M$_{1an}$ and M$_{1bn}$ of Figure 5.14-(ii)) in the NAND gate.

Although this effect also takes place in conventional CMOS technologies, it is worsened here due to the lower drain-source transconductance of the devices in the active region. This is a severe limitation in using complementary CMOS logic gates with many input variables. This can be seen in Figure 5.18, where a ring oscillator with the NAND of Figure 5.14 replaced by a 6-input NAND gate is simulated (all but one input - used in the feedback path - are connected to $V_{DD}$). We can see a strong degradation in the switching speed (in the fall time) due to the 6-input NAND gate.

One solution is the decomposition of functions with a large number of input variables, into simple sub-functions as in Figure 5.19. But the optimal solution is not trivial as, in turn, delays due to interconnections arise. The extra parasitic interconnect capacitances will also become an extra load that can slow-down the individual gates switching times. Only detailed simulations can determine the best design choices.

Figure 5.18: Transient simulation of a ring oscillator with 6-input NAND gate.

Figure 5.19: Decomposition of gates with a large number of inputs in smaller ones.

    

Footnotes

... ratio^145#3

For conventional technologies the problem is only to optimize the $I_{on}$ current, as $I_{off}$ is considered to be zero or negligible