As more and more three-dimensional process simulators become available, in the future, the natural tendency of the described tools will be the replacement of the two-dimensional simulators by those new ones. The gridding mechanism of the capacitance/resistance extraction simulators can be improved by using a fully unstructed three-dimensional mesh tool.
In the next two years high performance integrated circuits (e.g. microprocessors, telecommunication systems) are expected to operate with more than 1GHz clock frequency and having a total wire length exceeding 1Km! These factors will force interconnect analysis tools to incorporate electromagnetic phenomena. When the ratio of the signal wavelength over the critical path length approaches unity, new tools capable of solving the Maxwell's equations (at some degree of approximation) will be indispensable.
Large circuit simulations will probably always use lumped models of resistors, capacitor and inductances. But, many interconnection wires will require to be modeled with a ever large number of these elements. Research is necessary on optimal automatic insertion of this extra nodes and subsequent node reduction to generate accurate, yet simpler, interconnect macromodels.
At a digital circuit level there is plenty of work to do in searching for logic styles that are more robust against the large leakage currents of low-voltage technologies. New synthesis tools that avoid large series-connections of transistors either in static-logic or in the evaluation block in dynamic-logic are also necessary. In analog circuit design new compensation methods will become important as the same overall gain can only be achieved with more stages.