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Next: 9. Summary and Outlook Up: 8. Low-Voltage, Low-Power Operational Previous: 8.2 Ultra Low Voltage


8.3 Simulation Results

The layout of the circuit (shown in Figure 8.8) was designed with typical $0.5 \mu m$ technology rules. As the transistors are quite large (as usual in analog circuits), the three-dimensional model was created directly from the layout, and it is presented in Figure 8.9. The extracted parasitic capacitor values were added to the circuit netlist, and then the simulations were performed.

In Figure 8.10 we show the total transconductance error in the input stage (the error is normalized in relation to the transconductance when the input common mode voltage is 0.25V). It can be seen that the maximum absolute variation is within 15%, a value comparable with other designs [101][102].

Figure 8.10: Transconductance error of the input stage.
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Figure 8.12 displays the transient response for small-signals for a unitary gain in a non-inverting configuration (see Figure 8.11) and with the output loaded with a 5pF capacitor. If the overshoot (9%) is too high for a specific application, it can be reduced using a higher compensation capacitor at cost of bandwidth. We opted to favor this last parameter.

Figure 8.11: Non-inverting unitary gain amplifier.
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Figure 8.12: Transient response (gain= $\times 1$).
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The Figure 8.14 presents the transient response as a differential amplifier (see Figure 8.13) with a gain of $R_2/R_1 = 10$ for two input common mode voltages (0.25V and 0.0V). The output was also loaded with a 5pF capacitor. As we can see the response differences are small, only a maximum offset of 4.6mV exists, which demonstrates the efficiency of the constant $G_m$ circuitry. The mismatch in the onset are due to different initial conditions of the output voltage (that was made equal to the common voltage) and should not be considered.

Figure 8.13: Non-inverting unitary gain amplifier.
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Figure 8.14: Transient response to different common mode voltages (gain= $\times 10$).
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The total voltage gain is 1520 (64dB) for a 5MHz unit gain frequency. We agree that the gain is somewhat low, but this is a consequence of the reduced output resistance of transistors in these low-voltage technologies. For the time being the best choice, if gains around 60dB are too low for a given application, is to add more gain stages. In this case one must take care of the frequency stability and use more complex compensation techniques. Reference  [113] is a good source for solving this problem. Other important characteristics of the operational amplifier are summarized in Table 8.3.


Table 8.1: The most important operational amplifier characteristics.
Parameter Value
Power supply voltage 0.5 V
Input and output swing Rail-to-rail
Low frequency gain 64 dB
Unit-gain frequency 5 Mhz
Slew-rate 0.9 V/$\mu$s
Total power comsumption 15 $\mu$W (bias circuits not included)
Chip area 0.094 mm$^2$ (without bonding pads)


next up previous
Next: 9. Summary and Outlook Up: 8. Low-Voltage, Low-Power Operational Previous: 8.2 Ultra Low Voltage
Rui Martins
1999-02-24