8.2 Ultra Low Voltage Operational Amplifier Design

At 0.5V supply voltage the dynamic range it is at premium [100]. Every effort must be made to maximize its value, which compels the use of rail-to-rail input and output stages. From these, and assuming that the low-power requirements also exclude the tasks of driving heavily loaded loads, the input stage is the most critical.

A well known technique for realization of rail-to-rail input stage is to place two complementary differential pairs in parallel [101], as in Figure 8.1.

Figure 8.1: Rail-to-rail input stage.

When the input common mode voltage approaches the negative supply rail, the PMOS transistors are used and the NMOS transistors are off. A complementary behavior is achieved when the input common mode voltage approaches the positive supply rail, where the PMOS transistors are off. For intermediate common mode voltages both differential pairs are active and contribute to the overall gain of the stage.

Figure 8.2: Working ranges of the NMOS and PMOS differential pairs.

The NMOS pair operates for common mode voltages higher than (see Figure 8.2)

$$V_{cm,NMOS} > V_{SS} + V_{GS,M101} + V_{DS,M403}$$ (8.1)

and the PMOS pair for those lower than

$$V_{cm,PMOS} < V_{DD} + V_{GS,M201} + V_{DS,M304}$$ (8.2)

For rail-to-rail operation the power supply voltage must contain at least one $V_{cm,NMOS}$ plus one $V_{cm,PMOS}$. Therefore, the minimum power supply required is

$$V_{DD} - V_{SS} > 2V_{GS} + 2V_{DS} = 2V_{th} + 2V_{DS_{sat}}$$ (8.3)

When (8.3) is applied to a traditional technology (assumed to have a threshold voltage around 0.7V) replacing $V_{GS}$ by the threshold voltage and $V_{DS}$ by the minimum saturation voltage of the biasing transistor we obtain about 1.8V. Using very complex schemes to merge the two differential pairs, an operational amplifier capable of operating down to 1.3V (the absolute lowest voltage that can be achievable in such technologies) is reported in [102].

From these results becomes clear that a 0.5V operational amplifier only can be obtained when fabricated in technologies with much lower threshold voltages. Bipolar technology is also not a solution, as the base-emitter voltage must be at least 0.6V, greater than the 0.5V goal. For this technology a practical lower limit is 1.2V [103][104], about the same as in the conventional MOS case.

One method to reduce the threshold voltage is to bias the substrate and wells at voltages different from the power supply rails [105]. Yet, this reduction effect does not have a wide range and has associated problems, such as the need of several supply voltages and a more complicated wiring. Hence, a technology designed from the beginning to have a low threshold voltage performs better. As the technology described in Chapter 5 has a low threshold voltage, we use it in the design of the low-voltage operational amplifier. This technology was designed having in mind digital circuits, which is the usual case in technology development. The analog design must exhibit clever techniques to overcome the drawbacks of a technology with transistors optimized only for the maximum on/off drain current ratio.

As we reported a threshold voltage for this technology to be $V_{th}=0.25$V, the condition (8.3) is not verified. However, the threshold voltage definition in ultra-low-power technologies is not straightforward. Actually, in weak inversion the transistors can work at very low drain currents, and clearly afirming that the transistor is in the on or off state is not possible. In these cases, the classical definition of the threshold voltage as being the gate-source voltage at which an inversion channel forms and can thus conduct a high drain current [106] has no practical interest. From the definition used to establish a $V_{th}=0.25$V (see Section 5.2.3) one can notice that for a biasing current of $1\mu A$ it is possible to obtain gate-source voltages lower than $V_{th}$ if the width of the channel (W) is increased. Because of this, it is possible in this technology to design an operational amplifier (or other circuits) at a 0.5V power supply: The transistors need only to work in the weak inversion regime!

To achieve such low operating power supply voltages the number of drain-source series connections in the summing and following circuits must be reduced to a minimum: One for the biasing transistor and another for the gain transistor (see Figure 8.3-(i)). This excludes cascode configurations (see Figure 8.3-(ii)) used in [107] from the list of possible architectures. However, by doing so, we are trading gain for a reduced working voltage.

Figure 8.3: Amplifier stages: (i) Basic. (ii) Basic with cascode.

One problem of input stages with NMOS and PMOS differential pairs is that the two outputs must be summed and processed in such a way that the transconductance of the complete input stage is constant over the full input common mode range [108]. If this is not verified, it is not possible to optimize both noise and frequency compensation, the Common Mode Rejection Ratio (CMRR) is deteriorated and large signal distortion arises. Thus, it is very important to keep the total transconductance gain of the input stage ($G_m$) constant.

If no technique is adopted to automatically adjust the biasing currents ($I_{biasN}$ and $I_{biasP}$ in Figure 8.1) it is clear that $G_m$ will be doubled when the common mode is such that both pairs are in operation (in relation to when only one of them is active). Several techniques were reported to overcome this unacceptable high difference [101][102][109][110]. Most of these correspond to input stages working in strong inversion and use complicated biasing schemes. However, a much simpler solution exists if both differential pairs operate in weak inversion (or are made of bipolar transistors). In these cases the transconductance gain is proportional to the drain ($I_D$) [111] (or collector) current according to:

$$g_m = \frac{I_D}{nU_T}$$ (8.4)

where $n$ is the subthreshold slope factor (this applies only for MOSFETs), and $U_t = kT/q$ is the thermal voltage. So, by keeping the sum of $I_{biasN}+I_{biasP}$ constant, the total transconductance $G_m$ is constant as well.

Note that this procedure does not work when the input transistors are in strong inversion. In this case the transconductance is given by:

$$g_m = \sqrt{2 \beta I_D}$$ (8.5)

and a 40% higher transconductance will result in the situation where the biasing current is halved between the differential pairs.

Figure 8.4: Biasing circuit of the input stage.

This way, we can elegantly keep the total input transconductance constant by using the simple circuit of Figure 8.4 (the biasing circuitry is shown bold). In this circuit the main biasing current $I_{bias}$ (assumed to be constant) is splitted by the current switch $M_{401}$ between $I_{biasP}$ and $I_{aux}$, that is mirrored by transistors $M_{302}$ and $M_{303}$ to $I_{biasN}$. Therefore:

$$I_{bias} = I_{biasP} + I_{biasN} = Constant.$$ (8.6)

Clearly, when the input common mode voltage approaches ground, the gate-source voltage of the current switching transistor $M_{401}$ - $V_{GS,M401}$ is positive and this transistor is off forcing the NMOS input pair to be off as well. As the common mode voltage rises, $V_{GS,M401}$ decreases, becoming then becomes negative and $M_{401}$ starts to conduct. If the input common mode voltage continues to increase, it will at a certain point, conduct half of $I_{bias}$ and then more and more until, finally, its current equals $I_{bias}$ and the PMOS input pair is completely switched off. The turning point (where $I_{biasP} = I_{biasN}$) is determined by the voltage at AUX_BIAS. For NMOS and PMOS transistors with the same threshold voltage, AUX_BIAS must be settled so that the turning point is exactly half of the power supply voltage.

There are several ways to sum the output current of each differential pair. In the literature, cascoded configurations are usually used because they originate very high output impedances and consequently, an excellent voltage gain. Due to the already discussed reasons we searched for a simple technique. The simplest configuration would perhaps be that of Figure 8.5. Having it in mind, it can be seen that the drain-source voltages mismatch of the mirror transistors $M_{107}/M_{108}$ and $M_{207}/M_{208}$ depend on the output voltage that will have large variations. Unfortunately, the current mirrors working at very low biasing currents are not as good as when they are biased in deep strong inversion, causing this to be a severe inconvenience.

Figure 8.5: Simple summing circuit.

Moreover, the same applies to the input transistors whose drain-source voltage is also dependent on the output voltage. Therefore, the circuit in Figure 8.5 is poorly balanced, which brings several problems, such as large input offset voltages and a reduced dynamic range. A much better configuration is shown in Figure 8.6. Here the output node is not affecting the differential pair directly, so it can work almost perfectly balanced. The drawbacks are the higher number of transistors needed and the higher current consumption as there are more branches from $V_{DD}$ to $V_{SS}$. Nevertheless, one must note that this extra current is in the order of few micro-amperes, so the advantages of this configuration are worthwhile. Scaling the current mirrors $M_{103}/M_{106}$ and $M_{107}/M_{108}$ it is possible to reduce the drain current in $M_{106}$ and $M_{107}$ without unbalance the rest of the circuit, alleviating the above mentioned problem.

Figure 8.6: Schematic of the balanced operational amplifier.

Assuming that all current mirrors and matched transistors have the same channel length, the main design relations are the following:

$$Gain_{dc} = \frac{W_{105}}{W_{104}} \frac{1}{\lambda_{105} + \lambda_{108}} \frac{1}{n U_t};$$ (8.7)

$$Gain \times Bandwidth = GBW = I_{biasN} \frac{1}{2 n U_t} \frac{W_{105}}{W_{104}} \frac{1}{C_c};$$ (8.8)

$$Power = P = (1 + \frac{W_{106}}{2 W_{103}} + \frac{W_{105}}{2 W_{104}})I_{biasN} (V_{DD}-V_{SS)}.$$ (8.9)

$\lambda$ is the channel length modulation parameter, which in weak inversion may not necessarily be the same as if extracted from strong inversion measurements [112].

Another advantage of this configuration in relation to that in Figure 8.5 is a greater flexibility in design as (at the expense of a higher number of transistors) there is, besides the biasing current, one extra design parameter:  $W_{105}/W_{104}$.

To make the operational amplifier rail-to rail a twin amplifier (where each transistor is complementary) is superposed to that in Figure 8.6 with each input connected to the other input and both outputs short-circuited, as presented in Figure 8.7. Here, we can also see the biasing circuit of Figure 8.4 and a simple rail-to-rail output stage to further increase the total gain. To achieve stable operation a 10pF Miller compensation capacitor is added between the outputs of the second and first amplification stages.

Figure 8.7: Complete schematic of the low-voltage, low-power operational amplifier.

Figure 8.8: Layout of the low-voltage, low-power operational amplifier.

Figure 8.9: Three-dimensional structure of the low-voltage, low-power operational amplifier.