5.4 Fast Diffusivity Paths

Numerical simulations of electromigration are normally carried out on simple two-dimensional lines, in such a way that the effects of interfaces formed by the metal with the surrounding materials are frequently neglected. The most common example of such a case is the use of a single effective diffusion coefficient for the entire metal line, namely, for bulk, grain boundaries and interfaces.

Consider the interconnect via shown in Figure 5.18, where 0.01 V is applied at the left boundary of the upper line (M2) and 0.0 V at the right boundary of the lower line (M1). This yields a current density of 2 MA/cm$^2$ passing through the interconnect, and the electrons move from M1 to M2 (upstream electron flow). Figure 5.19 shows the current density in the line and via region. In this case, the electromigration development in the M2 line is studied.

Figure 5.18: Electric potential along the interconnect line (in V).

Figure 5.19: Current density distribution next to the via region (in MA/cm$^2$). The current density magnitude is larger in the via than in the line, since the cross section of the via is smaller than that of the line.

The current density is larger in the via than in the line, because the via has a smaller cross section than the line. This larger current density yields a higher joule heating in the via, which, in turn, leads to an increase of the temperature in this region, as shown in Figure 5.20. However, the external boundaries of the passivation are kept at the test temperature, 573 K, so that the temperature increase in the via is very small, and the entire interconnect practically remains at the same temperature. In fact, the temperature increase in the via is so small that it cannot significantly affect the vacancy transport.

Given the conditions above, vacancies are driven by electromigration from the left to the right end of the line. Since the bottom of the via is a blocking boundary, vacancies accumulate at this region, as shown in Figure 5.21. The increase in vacancy concentration at the via bottom is accompanied by the build-up of a tensile stress, shown in Figure 5.22.

Figure 5.20: Detail of the temperature distribution in the via region through a cut along the $x$ coordinate. A very small temperature increase in the via is caused by a higher joule heating in this region (in K).

Figure 5.21: Vacancy distribution in the M2 line and via after $100\,$h of electromigration test
(in cm$^{-3}$).

From these observations one can infer that void nucleation takes place at the bottom of the via. This void can further develop and span the via bottom, which certainly leads to a significant increase of the line resistance, thus triggering the interconnect failure. This failure mechanism has been observed in electromigration experiments of copper dual-damascene interconnects [8,114,163], where it is frequently called via failure.

Figure 5.22: Stress distribution in the via region through a cut along the $x$ coordinate after $100\,$h of electromigration test (in MPa).

Although such a failure mechanism has been experimentally detected, several other mechanisms have been identified. For example, in a group of papers, Vairagar et al. [27,31,32,114,164] showed that most of the failures occurred due to growth of a void initially located at the copper/capping layer interface at the cathode end of the line. In fact, they observed that a void initially nucleates at the copper/capping layer interface at a site away from the cathode end and migrates towards the cathode end. There, this void grows by coalescence with other incoming voids. Therefore, via failure corresponds to just a fraction of an entire failure population.

A similar situation appears, when the direction of current flow (downstream electron flow) is reversed and the EM behavior in the M1 line is investigated. In this case vacancies accumulate through the whole line thickness under the via and, consequently, a high tensile stress develops, as shown in Figure 5.23 and in Figure 5.24, respectively. Thus, void nucleation is expected to occur at this site, right underneath the via. Here again, a similar trend as that for the upstream case appears. Although void nucleation at such a location has been experimentally observed [24], voids are more often seen to nucleate at a site away from the via [31,32,114] and also adjacent to the via [24].

Figure 5.23: Vacancy distribution in the M1 line (downstream case) at $t = 100\,$h (in cm$^{-3}$). Vacancies concentrate right underneath the via.

Figure 5.24: Hydrostatic stress due to downstream electromigration at $t = 100\,$h (in MPa). The maximum stress is located right under the via.

From the discussion above one can see that using a single effective diffusivity value for the whole line can eventually explain some experimental findings. Nevertheless, several other observations cannot be described. For that purpose, a more meaningful and, at the same time, more realistic approach is required.

It is widely accepted that the interfaces between the copper and the typical SiN based capping layers are the dominant paths for diffusion in copper interconnects [3,13,70]. Therefore, it will be shown that it is extremely important to discriminate the diffusivities for each path along the interconnect, instead of using a single effective value as done in the previous section.

For a copper dual-damascene line the activation energy for diffusion is about 0.89 eV [13,159] along the copper/capping layer, about 1.2 eV [3,158] for diffusion along the copper/barrier interface, and 2.1 eV [3,158] for bulk diffusion. Applying these values in the simulations, the vacancy concentration and the stress distribution in the M2 line are shown in Figure 5.25 and in Figure 5.26, respectively.

Figure 5.25: Vacancy concentration, when the copper/capping layer interface is treated as a fast diffusivity path (in cm$^{-3}$). Vacancies concentrate at the copper/capping layer interface at the cathode end of the line.

Figure 5.26: The peak of hydrostatic stress is located at the copper/capping layer interface, when this interface acts as a fast diffusivity path (in MPa).

There is a small vacancy concentration build-up at the bottom of the via, however, the highest vacancy concentration is now located at the copper/capping layer interface at the cathode end of M2. The stress development follows the same trend. This is quite different compared to the results shown in the previous section, and is clearly a consequence of the higher diffusivity at the copper/capping layer interface. The high stress magnitude located at the copper/capping layer interface above the via can now explain the common experimental observation of void nucleation at such sites [8,31,32,114,164].

The vacancy concentration and the stress distribution for the downstream case are shown in Figure 5.27 and Figure 5.28, respectively. The main difference here is that the peak of the hydrostatic stress is not located right underneath the via, but is shifted to its edge, where there is an intersection between the copper, the capping layer, and the barrier layer. Since this intersection is likely to be a site of weak adhesion, void nucleation should occur at this edge, instead right underneath the via. This is in agreement with the observations commonly made in electromigration experiments [24].

Figure 5.27: Vacancy distribution for the downstream case (in cm$^{-3}$).

Figure 5.28: Hydrostatic stress distribution (in MPa). The peak of the stress is shifted to the left edge of the via, where copper, capping, and barrier layer intersect.

These simulation results show the importance of incorporating the fast diffusivity paths into the modeling approach, which can be conveniently carried out by setting the correct diffusion coefficient for the copper/capping layer interface, for the copper/barrier layer interface, and for the bulk. In this way, it is demonstrated that the simulation results match some typical experimental observations regarding the void nucleation sites and, consequently, failure development. Specifically, the failure triggered by void growth at the bottom of the via, as well as by void growth at the copper/capping layer interface at the cathode end of the line can be explained. Nevertheless, the common observation of void nucleation taking place away from the cathode end of the line still cannot be reproduced. The introduction of material interfaces as fast diffusivity paths alone does not suffice. These observations can only be explained by taking into account the effect of the microstructure on electromigration, as will be shown later.