When a sufficiently strong electric current passes through an interconnect metal, a diffusive motion of atoms and/or vacancies takes place in a direction along or opposite to the current flow. This phenomenon is called electromigration (EM) [1]. Although it had already been observed, EM became of practical interest in the late 1960's, when semiconductor companies observed EM failures in integrated circuits (ICs). Since then, failure due to EM has been one of the key issues regarding reliability in ICs.
The main goal of device scaling is to increase the operating speed. However, the interconnects pose a significant delay to signal propagation in a chip [2]. Therefore, device scaling should be accompanied by improvements in the interconnect operation. In order to reduce the delay, low interconnect resistance and capacitance is necessary, which demands high conductivity metals and interlayer materials with low permittivity. At the same time, efforts have been made in developing new integration processes and investigating materials which produce adequate characteristics and, ultimately, reduce the EM effect. These factors contributed to the substitution of aluminum as interconnect metal to aluminum-copper alloys, and later to pure copper [3]. Copper has a much higher electrical conductivity than aluminum and, moreover, is more resistant against EM failures. The introduction of copper metallizations posed several challenges which ultimately resulted in the damascene fabrication process [4].
According to the International Technology Roadmap for Semiconductors (ITRS) 2010 [5], the copper dual-damascene technology process will continue to be used for fabrication of on-chip interconnects for the next technological nodes.
The metal wiring pitch in integrated logic circuits is 64nm for the 32nm node, and will be 44nm for the 22nm node. At the same time, the expected operating current densities can reach 2.11MA/cm
and 2.80MA/cm, respectively.
The interconnect structure is arranged in several levels of metallization with thousands of interlevel connections such as vias, so that the density of on-chip interconnects has increased from generation to generation of modern integrated circuits. This requires a decrease in both interconnect width and thickness and, consequently, the operating current densities increase. Due to the continuous shrinking of interconnect dimensions, high current densities and temperatures are unavoidable. Therefore, electromigration failure is likely to be even more problematic for the next generations of ICs, and the prediction of the long term interconnect behavior is a major necessity.