2.2 Lateral High-Voltage Devices for Smart Power Applications

In a high-voltage and smart power circuitry, a wide variety of power devices is needed to obtain proper device characteristics for different applications. It is important to investigate the structure and device characteristics of these different kinds of power devices. Conventionally, lateral power semiconductor devices such as LDMOSFETs and LIGBTs are widely used for output devices in high-voltage and smart power ICs instead of vertical power devices so as to be compatible with low-voltage IC circuitry [50,80,81,82,83,84,85]. Output power semiconductors are used as switches, and the requirements for them include low on-state voltage drop to minimize conduction loss, high current density to reduce the chip size, high input impedance for ease of drive, fast turn-off to minimize switching loss, and finally a large safe operating area (SOA) [86,41,87]. To achieve these characteristics, proper device design and optimization are needed. For lateral power devices the RESURF principle (see details in Chapter 2.2) is generally used to obtain a fully depleted area at the drift region during blocking state. A field plate can also help to reduce the peak electric field at the gate edge. The RESURF principle utilizes a lightly doped substrate along with a thin epitaxial layer to block high-voltage.

Figure 2.8 shows a cross section of a conventional and a RESURF diode structure. When the depletion region moves towards the surface of the device, it will interact with the depletion region of the $p$-well and $n$-junction, and the total effect is that the depletion edge moves towards the $n^+$-region, leading to a strong reduction in the surface electric field. This condition is true if the length of the drift region is much larger than the thickness of the drift region. So the applied reverse voltage is laterally almost equally distributed along the surface and the peak electric field is forced to be in the bulk junction, and the breakdown can therefore be achieved when the horizontal junction breaks down. This makes it possible for lateral power devices to block a high-voltage even with a thin epitaxial layer.

Figure 2.8: Cross section of the conventional and RESURF diodes.

For the fabrication of power MOSFET a double diffusion process is used to diffuse phosphorus and boron sequentially from the same window opening (normally polysilicon gate). The difference between the lateral junction depth of two diffusions determines the channel length (see Figure 2.9 (a)). By this method a relatively short channel can be obtained without demanding submicron design rules. Figure 2.9 shows the concept of double diffusion and field plate. Electric isolation between power devices and low-voltage circuitry is a key issue for smart power ICs. There are basically three methods used for the isolation: self-isolation junction isolation and dielectric isolation. In self-isolation, the separation of low-voltage and high-voltage components is achieved by adopting the layout of the circuit and the nature of the bias. If the $p$-substrate is grounded, all body diodes are reverse biased, which provides the isolation needed. A high-voltage region can exist in this technology if the high field region is restricted to a closed-loop region. Junction isolation uses a designated layer of a reverse biased junction for isolation, its cost is higher than that of the self-isolation, but comparable with standard bipolar process. Dielectric isolation uses a dielectric layer such as buried oxide for isolation. In the following section several novel CMOS compatible lateral power devices are discussed, including lateral DMOSFETs, lateral IGBTs, lateral MCTs, and double gate lateral MCTs.

Figure 2.9: Double diffusion and field plate.