2.2.1 Lateral DMOSFETs

In recent years lateral double-diffused MOS transistors (LDMOSFETs) have become the preferred devices for monolithic high-voltage and smart power applications. The advantages over VDMOSFETs are a reduction in the number of fabrication steps, multiple output capability on the same chip and compatibility with advanced VLSI technologies. LDMOSFETs with VLSI processes make the prospect of intelligent power ICs a reality. There are two major categories of LDMOS devices. One is a conventional LDMOSFET, and the other is a RESURF LDMOSFET (hereafter LDMOSFET). To obtain best device characteristics the drift doping concentration must be controlled carefully, but RESURF technology has a better on-state performance compared to the conventional approach for the same breakdown voltage.

Figure 2.10 shows the cross section of the LDMOSFET structure. Normally, LDMOSFETs can be made in an optimized $n$-type epitaxial layer, and deep $p$-type diffused regions are used to isolate them.

Figure 2.10: Cross section of the LDMOSFET.

The standard $n$-type and $p$-type source and drain regions are used for contacting source/drain and body, respectively. The LDMOSFET has three major serial resistance components, the metal resistance, the channel resistance, and the drift region resistance. For high-voltage LDMOSFETs the dominant part among them is the drift resistance, and there is a trade-off between the breakdown voltage and the resistance of the drift region. Another interesting aspect of the LDMOSFET is the channel formed by lateral double diffusion. The effective channel length is defined by the difference in the lateral diffusions of the $p$-body and the $n^+$-source regions. The lateral diffusion depth is normally 60 - 85$\%$ of the vertical diffusion depth. This means that the effective channel length is fixed for a given process (depending on the vertical junction depth and doping concentration), and a nonuniform doping concentration can be seen inside the channel region.

If the channel and the source of the LDMOSFET are isolated from the $p$-substrate, the thickness of the $n$-epitaxial layer $t_\mathrm{epi}$ must be chosen such that punchthrough between source and substrate does not occur before avalanche breakdown. In the case shown in Figure 2.10 the channel is grounded through the $p$-substrate, and it is not necessary to consider this constraint (punchthrough between source and substrate) in this structure. A minimum channel length $L_\mathrm{min}$ must be ensured to prevent punchthrough between drain and source. Assuming that the $p$-well and the $n$-drift junction has a linearly graded junction in the channel side and abrupt in the drift region of the junction, the depletion layer width in the channel is given by

$$W_\mathrm{PT(ch)} = ({\frac{3\varepsilon_{si}}{q\,S}}V_\mathrm{PT})^{\frac{1}{3}}\,,$$ (2.1)

where $G$ is the slope of the graded junction ($p$-well and $n$-drift junction) and $V_\mathrm{PT}$ is the reverse voltage at punchthrough. Roughly the slope $S$ at the $p$-well and $n$-drift junction in Figure 2.10 is defined as the ratio of the difference between the $p$-well doping concentrations at the boundaries of the channel to the channel length at punchthrough (minimum channel length $L_\mathrm{min}$)

$$S = \frac{N_\mathrm{ch(source)} - N_\mathrm{ch(drift)}}{L_\mathrm{min}}\,,$$ (2.2)

where $N_\mathrm{ch(source)}$ is the doping concentration at the source end and $N_\mathrm{ch(drift)}$ is that at the drift end. Assuming the punchthrough condition is reached when the channel becomes completely depleted by the drift junction, the minimum channel length required to avoid punchthrough is given by

$$L_\mathrm{min} = W_\mathrm{PT(ch)} = ({\frac{3\varepsilon_{si}}{q\,S}}\,V_\mathrm{PT})^{\frac{1}{3}}\,.$$ (2.3)

Replacing $S$ in (2.3) by the expression given in (2.2), the resulting minimum channel length can be expressed as

$$L_\mathrm{min} =\sqrt{\frac{3\varepsilon_{si}\,V_\mathrm{PT}}{q\,(N_\mathrm{ch(source)} - N_\mathrm{ch(drift)})}}\,.$$ (2.4)

It should be noted that peak of the doping concentration is not located at the source end, but slightly shifted into the channel. The doping concentration to control the threshold voltage of the device must be considered to determine the minimum channel length.

The drift length $L_\mathrm{d}$ in Figure 2.10 and the doping concentration $N_\mathrm{d}$ of the drift region are the most important parameters to determine the device characteristics. If a high voltage is applied at the drain of the LDMOSFET, most of the voltage drops in this region. To obtain a higher breakdown voltage the drift region must be completely depleted according to the RESURF principle (see Figure 2.8 (b)). However a simple extension of the drift length $L_\mathrm{d}$ is not sufficient to increase the breakdown voltage. Because of the surface effects a high electric field is focused at the surface of the $n$-drift and $p$-well junction, avalanche breakdown will occur at this place. Because the lateral diffusion has been found to extend to about 60$\%$ to 85$\%$ of the vertical depth, the junction curvature near the surface is larger compared to that at the corner of the bulk junction. It causes a higher electric field at the surface of the junction. A field plate at the gate region helps to overcome these surface effects. Two-dimensional simulation results with these parameters will be shown in Chapter 4.

Figure 2.11: Cross section of the SOI-LDMOSFET.

LDMOSFETs can be implemented in bulk silicon or SOI [88,89,90,91,92]. SOI-LDMOSFETs constitute an attractive alternative to conventional JI-LDMOSFETs, because the isolation area between devices shrinks and lower leakage currents result in greatly improved high temperature performance.

Figure 2.11 shows a cross-sectional view of an $n$-channel SOI-LDMOSFET. The BV of an SOI structure is a function of the thickness of the silicon and the buried oxide layer [93,94,95,96,97,98,99,100,101,102]. The buried oxide helps to sustain a high electric field which results in a higher BV. The operation of SOI power devices is limited by self-heating effects during switching and some fault conditions such as short circuit [103,104,105]. Since the buried oxide underneath the device is a good thermal insulator, the temperature rise inside SOI power devices can be much higher than that of bulk silicon devices. It will be shown in Chapter 4 how to overcome self-heating inherent in SOI devices.